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UPA1911TE-A

更新时间： 2024-01-15 16:27:47
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管场效应晶体管开关
页数 文件大小 规格书
8页 67K
描述
Small Signal Field-Effect Transistor, 2.5A I(D), 20V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, MINIMOLD PACKAGE-6

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UPA1911TE-A 技术参数

是否Rohs认证：符合生命周期：Obsolete
包装说明：SMALL OUTLINE, R-PDSO-G6针数：6
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8541.21.00.95风险等级：5.32
Is Samacsys：N配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：20 V最大漏极电流 (Abs) (ID)：2.5 A
最大漏极电流 (ID)：2.5 A最大漏源导通电阻：0.12 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PDSO-G6
JESD-609代码：e6元件数量：1
端子数量：6工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：P-CHANNEL
最大功率耗散 (Abs)：2 W认证状态：Not Qualified
子类别：Other Transistors表面贴装：YES
端子面层：Tin/Bismuth (Sn98Bi2)端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

UPA1911TE-A 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
PA1911  
µ
P-CHANNEL MOS FIELD EFFECT TRANSISTOR  
FOR SWITCHING  
DESCRIPTION  
PACKAGE DRAWING (Unit : mm)  
The µPA1911 is a switching device which can be driven  
+0.1  
–0.05  
+0.1  
–0.06  
0.32  
0.16  
-
directly by a 2.5 V power source.  
The µPA1911 features a low on-state resistance and excellent  
switching characteristics, and is suitable for applications such  
as power switch of portable machine and so on.  
6
1
5
2
4
3
0 to 0.1  
FEATURES  
-
• Can be driven by a 2.5 V power source  
• Low on-state resistance  
0.65  
0.95 0.95  
1.9  
DS(on)1  
R
DS(on)2  
R
DS(on)3  
R
GS  
D
= 115 mΩ MAX. (V = –4.5 V, I = –1.5 A)  
GS  
D
= 120 mΩ MAX. (V = –4.0 V, I = –1.5 A)  
0.9 to 1.1  
2.9 ±0.2  
GS  
D
= 190 mΩ MAX. (V = –2.5 V, I = –1.0A)  
1, 2, 5, 6 : Drain  
3
4
: Gate  
: Source  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
EQUIVALENT CIRCUIT  
µPA1911TE  
6-pin Mini Mold (Thin Type)  
Drain  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Body  
Diode  
DSS  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current (DC)  
Drain Current (pulse) Note1  
Total Power Dissipation  
Total Power Dissipation Note2  
Channel Temperature  
Storage Temperature  
V
V
–20  
–12/+6  
# 2.5  
# 10  
0.2  
V
Gate  
GSS  
V
A
D(DC)  
Gate  
Protection  
Diode  
I
D(pulse)  
I
A
Source  
T1  
P
W
W
°C  
Marking: TC  
T2  
P
2
ch  
T
150  
stg  
T
–55 to +150 °C  
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %  
2. Mounted on FR-4 board, t ≤ 5 sec.  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage  
exceeding the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
D13455EJ1V0DS00 (1st edition)  
Date Published September 1999 NS CP(K)  
Printed in Japan  
1998, 1999  
©
12345678

中文翻译

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