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UPA1912TE

更新时间： 2024-11-18 22:41:43
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管场效应晶体管开关
页数 文件大小 规格书
8页 61K
描述
P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING

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中文翻译

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UPA1912TE 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SC-95包装说明：THIN, MINIMOLD, SC-95, 6 PIN
针数：6Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8541.21.00.95
风险等级：5.32其他特性：ESD PROTECTED
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：12 V
最大漏极电流 (ID)：4.5 A最大漏源导通电阻：0.07 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PDSO-G6
JESD-609代码：e0元件数量：1
端子数量：6工作模式：ENHANCEMENT MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：P-CHANNEL认证状态：Not Qualified
表面贴装：YES端子面层：TIN LEAD
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICON

UPA1912TE 数据手册

 浏览型号UPA1912TE的Datasheet PDF文件第2页浏览型号UPA1912TE的Datasheet PDF文件第3页浏览型号UPA1912TE的Datasheet PDF文件第4页浏览型号UPA1912TE的Datasheet PDF文件第5页浏览型号UPA1912TE的Datasheet PDF文件第6页浏览型号UPA1912TE的Datasheet PDF文件第7页 
DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
PA1912  
µ
P-CHANNEL MOS FIELD EFFECT TRANSISTOR  
FOR SWITCHING  
DESCRIPTION  
PACKAGE DRAWING (Unit : mm)  
The µPA1912 is a switching device which can be driven  
directly by a 2.5-V power source.  
+0.1  
–0.05  
+0.1  
–0.06  
0.32  
0.16  
The µPA1912 features a low on-state resistance and excellent  
switching characteristics, and is suitable for applications such  
as power switch of portable machine and so on.  
6
1
5
2
4
3
0 to 0.1  
FEATURES  
• Can be driven by a 2.5-V power source  
• Low on-state resistance  
0.65  
0.95 0.95  
1.9  
DS(on)1  
R
DS(on)2  
R
DS(on)3  
R
GS  
D
= 50 mΩ MAX. (V = –4.5 V, I = –2.5 A)  
0.9 to 1.1  
2.9 ±0.2  
GS  
D
= 52 mΩ MAX. (V = –4.0 V, I = –2.5 A)  
GS  
D
= 70 mΩ MAX. (V = –2.5 V, I = –2.5 A)  
1
, 2, 5, 6 : Drain  
3
4
: Gate  
: Source  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
6-pin Mini Mold (Thin Type)  
EQUIVALENT CIRCUIT  
µPA1912TE  
Drain  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Body  
Diode  
DSS  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current (DC)  
Drain Current (pulse) Note1  
Total Power Dissipation  
Total Power Dissipation Note2  
Channel Temperature  
Storage Temperature  
V
V
–12  
±10  
±4.5  
±18  
0.2  
2
V
Gate  
GSS  
V
A
Gate  
Protection  
Diode  
D(DC)  
I
D(pulse)  
I
A
Source  
T1  
P
W
W
°C  
Marking: TD  
T2  
P
ch  
T
150  
stg  
T
–55 to +150 °C  
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %  
2. Mounted on FR-4 board, t ≤ 5 sec.  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage  
exceeding the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published July 1999 NS CP(K)  
Printed in Japan  
D13806EJ2V0DS00 (2nd edition)  
The mark ★ shows major revised points.  
1998, 1999  
©
12345678

中文翻译

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