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UL62H256AS2K55G1 PDF预览

UL62H256AS2K55G1

更新时间: 2024-11-13 03:23:39
品牌 Logo 应用领域
ZMD 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 162K
描述
Low Voltage Automotive Fast 32K x 8 SRAM

UL62H256AS2K55G1 数据手册

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UL62H256A  
Low Voltage Automotive Fast 32K x 8 SRAM  
Features  
Description  
! 32768 x 8 bit static CMOS RAM  
! 35 and 55 ns Access Time  
! Common data inputs and  
data outputs  
The UL62H256A is a static RAM  
go High-Z until the new information  
is available. The data outputs have  
no preferred state. The Read cycle  
is finished by the falling edge of W,  
or by the rising edge of E, respec-  
tively.  
manufactured using a CMOS pro-  
cess technology with the following  
operating modes:  
! Three-state outputs  
! Typ. operating supply current  
35 ns: 45 mA  
- Read  
- Write  
- Standby  
- Data Retention  
The memory array is based on a  
6-Transistor cell.  
Data retention is guaranteed down  
to 2 V. With the exception of E, all  
inputs consist of NOR gates, so  
that no pull-up/pull-down resistors  
are required.  
55 ns: 30 mA  
! Standby current < 40 µA at 125 °C The circuit is activated by the fal-  
! TTL/CMOS-compatible  
! Power supply voltage 2.5 - 3.6 V  
! Operating temperature range  
-40 °C to 85 °C  
ling edge of E. The address and  
control inputs open simultaneously.  
According to the information of W  
and G, the data inputs, or outputs,  
are active. In a Read cycle, the  
data outputs are activated by the  
falling edge of G, afterwards the  
data word will be available at the  
outputs DQ0-DQ7. After the  
address change, the data outputs  
-40 °C to 125 °C  
! QS 9000 Quality Standard  
! ESD protection > 2000 V  
(MIL STD 883C M3015.7)  
! Latch-up immunity >100 mA  
! Package: SOP28 (300/330 mil)  
Pin Configuration  
Pin Description  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
A14  
A12  
A7  
2
W
3
A13  
A8  
A6  
4
Signal Name Signal Description  
A5  
5
A9  
A0 - A14  
DQ0 - DQ7  
Address Inputs  
Data In/Out  
A4  
6
A11  
A3  
7
G
Chip Enable  
Output Enable  
Write Enable  
E
G
W
SOP  
A2  
8
A10  
A1  
9
E
DQ7  
Power Supply  
A0  
10  
11  
12  
13  
14  
VCC  
VSS  
Voltage  
DQ0  
DQ1  
DQ2  
VSS  
DQ6  
DQ5  
DQ4  
DQ3  
Ground  
Top View  
May 07, 2004  
1

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