Datasheet > UL62H256BS1K55

UL62H256BS1K55

更新时间： 2024-11-14 04:19:43

品牌	Logo	应用领域
SIMTEK		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
9页	82K
描述
Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP-28

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数据手册

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UL62H256BS1K55 数据手册

UL62H256B

Low Voltage Automotive Fast 32K x 8 SRAM

Features

Description

The UL62H256B is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

F 32768 x 8 bit static CMOS RAM

F 35 and 55 ns Access Time

F Common data inputs and

data outputs

address change, the data outputs

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 1.5 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

F Three-state outputs

F Typ. operating supply current

35 ns: 45 mA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

55 ns: 30 mA

F Standby current < 30 µA at 125 °C The circuit is activated by the fal-

F Power supply voltage 2.5 V

F Operating temperature range

-40 °C to 85 °C

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word will be available at the

outputs DQ0-DQ7. After the

-40 °C to 125 °C

F CECC 90000 Quality Standard

F ESD protection > 2000 V

(MIL STD 883C M3015.7)

F Latch-up immunity >100 mA

F Package: SOP28 (300/330 mil)

Pin Description

Pin Configuration

VCC

A14

A12

A13

Signal Name Signal Description

A0 - A14

Address Inputs

Data In/Out

A11

DQ0 - DQ7

Chip Enable

A10

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

DQ7

VCC

VSS

DQ0

DQ1

DQ2

VSS

DQ6

DQ5

DQ4

DQ3

Top View

September 26, 2002

12 3 4 5 6 7...9

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