Datasheet > UD61256DC08

UD61256DC08

更新时间： 2024-11-17 21:54:07

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
13页	224K
描述
256K x 1 DRAM

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中文翻译

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数据手册

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UD61256DC08 数据手册

Maintenance only

UD61256

256K x 1 DRAM

Data Output Control

Features

Description

The usual state of the data output is

the High-Z state. Whenever CAS is

Dynamic random access memory Addressing

262144 x 1 bit manufactured

using a CMOS technology

RAS access times 70 ns, 80 ns

TTL-compatible

Three-state output

256 refresh cycles

The UD61256 is a dynamic Write- inactive (HIGH), Q will float (High-Z).

Read-memory with random access. Thus, CAS functions as data output

FPM facilitates faster data operation control.

with predefined row address. Via 9 After access time, in case of a Read

address inputs the 18 address bits cycle, the output is activated, and it

are transmitted into the internal contains the logic „0“ or „1“.

address memories in a time-multi- Q is then valid until CAS returns into

plex operation. The falling RAS- to inactive state (HIGH).

4 ms refresh cycle time

FAST PAGE MODE

Operating modes: Read, Write,

Read - Write,

edge takes over the row address. The memory cycle being a Read,

During RAS Low, the column Read-Write or a Write cycle (W-con-

RAS only Refresh,

address together with the CAS trolled), Q changes from High-Z

Hidden Refresh with address

transfer

Power Supply Voltage 5 V

signal are taken over. The selection state to the active state („0“ or „1“).

of one or more memory circuits can After the access time the contents of

be made by activation of the RAS the selected cell is available, except

Packages PDIP16 (300 mil) input.

SOJ20/26 (300 mil)

for the Write cycle.

The output remains active until CAS

Operating temperature range

0 to 70 °C

Read-Write-Control

The choice between Read or Write RAS becoming inactive or not. The

becomes inactive, irrespective of

Quality assessment according to cycle is made at the W input. HIGH memory cycle being a Write cycle

CECC 90000, CECC 90100 and at the W input causes a Read cycle, (CAS-controlled), the data output

CECC 90112

meanwhile LOW leads to a Write keeps its High-Z state throughout

cycle. the whole cycle. This configuration

Both CAS-controlled and W-control- makes Q fully controllable by the

led Write cycles are possible with user merely through the timing of W.

activated RAS signal.

The output storaging the data, they

remain valid from the end of access

time until the start of another cycle.

Pin Description

Pin Configuration

Signal Name Signal Description

VSS

A0 - A8

Address Inputs

Data Input

CAS

Read, Write Control

Row Address Strobe

Power Supply Voltage

Ground

n.c.

RAS

n.c.

RAS

UCC

USS

CAS

RAS

PDIP

Column Address Strobe

Data Output

SOJ

n.c.

no connected

VCC

n.c.

Top View

VCC

Top View

December 12, 1997

12 3 4 5 6 7...13

中文翻译

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与UD61256DC08相关器件

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UD61256JC08	ETC	获取价格	256K x 1 DRAM
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UD61466DC08	ZMD	获取价格	64K x 4 DRAM
UD6604-H	UTC	获取价格	complementary
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