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UD61466DC07 PDF预览

UD61466DC07

更新时间： 2024-01-05 06:59:49
品牌 Logo 应用领域
ZMD 内存集成电路静态存储器光电二极管动态存储器
页数 文件大小 规格书
14页 175K
描述
64K x 4 DRAM

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UD61466DC07 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP18,.3
针数：18Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.92Is Samacsys：N
访问模式：STATIC COLUMN最长访问时间：70 ns
I/O 类型：COMMONJESD-30 代码：R-PDIP-T18
JESD-609代码：e0长度：23.4 mm
内存密度：262144 bit内存集成电路类型：STATIC COLUMN DRAM
内存宽度：4功能数量：1
端口数量：1端子数量：18
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX4
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP18,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified刷新周期：256
座面最大高度：5.1 mm子类别：SRAMs
最大压摆率：0.07 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

UD61466DC07 数据手册

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Maintenance only  
UD61466  
64K x 4 DRAM  
SCM facilitates faster data operation Data Output Control  
Features  
with predefined row address. Via 8  
address inputs the 16 address bits  
are transmitted into the internal  
address memories in a time-multi-  
plex operation. The falling RAS-  
edge takes over the row address.  
After the row address hold time the  
column address can be applied.  
During the Read cycle the address  
transfer is not latched by the falling  
edge at the CAS input, so that the  
column address must be applied  
until the data are valid at the output.  
During Write the column address is  
taken over with the falling edge of  
the control signal CAS, or W, that  
becomes active as the last. The sel-  
ection of one or more memory cir-  
cuits can be made via the RAS  
input.  
The usual state of the data output is  
the High-Z state. Whenever CAS is  
inactive (HIGH), Q will float (High-Z).  
Thus, CAS functions as data output  
control.  
After access time, in case of a Read  
cycle, the output is activated, and it  
contains the logic „0“ or „1“.  
Dynamic random access memory  
65536 x 4 bits manufactured  
using a CMOS technology  
RAS access times 70 ns/80 ns  
TTL-compatible  
Three-state outputs bidirectional  
256 refresh cycles  
4 ms refresh cycle time  
STATIC COLUMN MODE  
Operating modes: Read, Write,  
Read - Write,  
RAS only Refresh,  
Hidden Refresh with address  
transfer  
Low power dissipation  
Power supply voltage 5 V  
Package PDIP18 (300 mil)  
Operating temperature range  
0 to 70 °C  
The memory cycle being a Read,  
Read-Write or a Write cycle (W-con-  
trolled),  
Q changes from High-Z  
state to the active state („0“ or „1“).  
After access time, the contents of  
the selected cell will be available,  
with the exception of the Write cycle.  
The output remains active until CAS  
becomes inactive, irrespective of  
RAS becoming inactive or not. The  
memory cycle being a Write cycle  
(CAS-controlled), the data output  
keeps its High-Z state throughout  
the whole cycle. This configuration  
Quality assessment according to  
CECC 90000, CECC 90100 and Read-Write-Control  
CECC 90112  
The choice between Read or Write makes Q fully controllable by the  
cycle is made at the W input. HIGH user merely through the timing of W.  
at the W input causes a Read cycle, The output storaging the data, they  
meanwhile LOW leads to a Write remain valid from the end of access  
Description  
Addressing  
cycle.  
time until the start of another cycle.  
The UD61466 is a dynamic random Both CAS-controlled and W-control-  
access memory organized 65536 led Write cycles are possible with  
words by 4 bits.  
activated RAS signal.  
Pin Description  
Pin Configuration  
1
2
3
4
5
6
7
8
9
VSS  
DQ3  
CAS  
DQ2  
A6  
(OE)  
(WE)  
G
DQ0  
DQ1  
W
18  
17  
16  
15  
14  
13  
12  
11  
10  
Signal Name Signal Description  
A0 - A7  
Address Inputs  
DQ0 - DQ3  
Data In/Out  
Read, Write Control  
Row Address Strobe  
Output Enable  
W
PDIP  
SOJ  
RAS  
A0  
RAS  
G
A3  
A4  
A2  
VCC  
VSS  
CAS  
Power Supply Voltage  
Ground  
A5  
A1  
A7  
VCC  
Column Address Strobe  
Top View  
1
December 12, 1997  
1234567...14

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