Maintenance only
UD61256
256K x 1 DRAM
Data Output Control
Features
Description
The usual state of the data output is
the High-Z state. Whenever CAS is
Dynamic random access memory Addressing
262144 x 1 bit manufactured
using a CMOS technology
RAS access times 70 ns, 80 ns
TTL-compatible
Three-state output
256 refresh cycles
The UD61256 is a dynamic Write- inactive (HIGH), Q will float (High-Z).
Read-memory with random access. Thus, CAS functions as data output
FPM facilitates faster data operation control.
with predefined row address. Via 9 After access time, in case of a Read
address inputs the 18 address bits cycle, the output is activated, and it
are transmitted into the internal contains the logic „0“ or „1“.
address memories in a time-multi- Q is then valid until CAS returns into
plex operation. The falling RAS- to inactive state (HIGH).
4 ms refresh cycle time
FAST PAGE MODE
Operating modes: Read, Write,
Read - Write,
edge takes over the row address. The memory cycle being a Read,
During RAS Low, the column Read-Write or a Write cycle (W-con-
RAS only Refresh,
address together with the CAS trolled), Q changes from High-Z
Hidden Refresh with address
transfer
Power Supply Voltage 5 V
signal are taken over. The selection state to the active state („0“ or „1“).
of one or more memory circuits can After the access time the contents of
be made by activation of the RAS the selected cell is available, except
Packages PDIP16 (300 mil) input.
SOJ20/26 (300 mil)
for the Write cycle.
The output remains active until CAS
Operating temperature range
0 to 70 °C
Read-Write-Control
The choice between Read or Write RAS becoming inactive or not. The
becomes inactive, irrespective of
Quality assessment according to cycle is made at the W input. HIGH memory cycle being a Write cycle
CECC 90000, CECC 90100 and at the W input causes a Read cycle, (CAS-controlled), the data output
CECC 90112
meanwhile LOW leads to a Write keeps its High-Z state throughout
cycle. the whole cycle. This configuration
Both CAS-controlled and W-control- makes Q fully controllable by the
led Write cycles are possible with user merely through the timing of W.
activated RAS signal.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
Pin Description
Pin Configuration
Signal Name Signal Description
1
2
3
4
5
V
26
25
24
23
22
A8
D
VSS
1
2
3
4
5
6
7
8
A8
D
16
15
14
13
12
11
10
9
A0 - A8
D
Address Inputs
Data Input
CAS
Q
CAS
Q
W
Read, Write Control
Row Address Strobe
Power Supply Voltage
Ground
W
W
A6
n.c.
RAS
n.c.
RAS
UCC
USS
CAS
Q
A6
A3
A4
A5
A7
RAS
PDIP
A0
A2
Column Address Strobe
Data Output
SOJ
A1
n.c.
no connected
VCC
n.c.
A0
9
18
17
16
15
14
n.c.
A3
A4
A5
A7
10
11
12
13
Top View
A2
A1
VCC
Top View
December 12, 1997
1
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
