Datasheet > UD61464DC07

UD61464DC07

更新时间： 2024-11-17 23:39:07

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
14页	176K
描述
x4 Fast Page Mode DRAM

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中文翻译

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数据手册

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UD61464DC07 数据手册

Maintenance only

UD61464

64K x 4 DRAM

Features

FPM facilitates faster data operation Data Output Control

with predefined row address. Via 8

address inputs the 16 address bits

are transmitted into the internal

address memories in a time-multi-

plex operation. The falling RAS-

edge takes over the row address.

After the row address hold time the

column address can be applied. The

bit pattern that is available at the

address outputs during the set-up

time and after the falling edge of

CAS is interpreted as row address.

During Write the column address is

taken over with the falling edge of

the control signal CAS, or W, whi-

chever becomes active as the last.

The selection of one or more

memory circuits can be made via the

RAS input.

The usual state of the data output is

the High-Z state. Whenever CAS is

inactive (HIGH), Q will float (High-Z).

Thus, CAS functions as data output

control.

After access time, in case of a Read

cycle, the output is activated, and it

contains the logic „0“ or „1“.

Dynamic random access memory

65536 x 4 bits manufactured

using a CMOS technology

RAS access times 70 ns/80 ns

TTL-compatible

Three-state outputs bidirectional

256 refresh cycles

4 ms refresh cycle time

FAST PAGE MODE

Operating modes: Read, Write,

Read - Write,

RAS only Refresh,

Hidden Refresh with address

transfer

If the memory cycle is a Read,

Read-Write or a Write cycle (W-con-

trolled), Q changes from High-Z

state to the active state („0“ or „1“).

After access time, the contents of

the selected cell will be available,

with the exception of the Write cycle.

The output remains active until CAS

becomes inactive, irrespective of

RAS becoming inactive or not. The

memory cycle being a Write cycle

(CAS-controlled), the data output

keeps its High-Z state throughout

Low power dissipation

Power supply voltage 5 V

Package PDIP18 (300 mil)

Operating temperature range

0 to 70 °C

Quality assessment according to Read-Write-Control

CECC 90000, CECC 90100 and The choice between Read or Write the whole cycle. This configuration

CECC 90112

cycle is made at the W input. HIGH makes Q fully controllable by the

at the W input causes a Read cycle, user merely through the timing of W.

meanwhile LOW leads to a Write Through storaging the data on out-

Description

cycle.

put, they remain valid from the end

Addressing

Both CAS-controlled and W-control- of access time until the start of

The UD61464 is a dynamic random led Write cycles are possible with another cycle.

access memory organized 65536 activated RAS signal.

words by 4 bits.

Pin Configuration

Pin Description

Signal Name Signal Description

VSS

DQ3

CAS

DQ2

(OE)

(WE)

DQ0

DQ1

A0 - A7

Address Inputs

DQ0 - DQ3

Data In/Out

Read, Write Control

Row Address Strobe

Output Enable

RAS

PDIP

VCC

VSS

CAS

Power Supply Voltage

Ground

Column Address Strobe

VCC

Top View

December 12, 1997

12 3 4 5 6 7...14

中文翻译

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与UD61464DC07相关器件

型号	品牌	获取价格	描述	数据表
UD61464DC08	ETC	获取价格	x4 Fast Page Mode DRAM
UD61466	ZMD	获取价格	64K x 4 DRAM
UD61466DC07	ZMD	获取价格	64K x 4 DRAM
UD61466DC08	ZMD	获取价格	64K x 4 DRAM
UD6604-H	UTC	获取价格	complementary
UD6KB05	MCC	获取价格	6 Amp Glass Passivated Bridge Rectifier 50 to 1000 Volts
UD6KB10	MCC	获取价格	6 Amp Glass Passivated Bridge Rectifier 50 to 1000 Volts
UD6KB100	MCC	获取价格	6 Amp Glass Passivated Bridge Rectifier 50 to 1000 Volts
UD6KB20	MCC	获取价格	6 Amp Glass Passivated Bridge Rectifier 50 to 1000 Volts
UD6KB40	MCC	获取价格	6 Amp Glass Passivated Bridge Rectifier 50 to 1000 Volts

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