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UD61464DC08

更新时间： 2024-01-31 08:17:07
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
14页 176K
描述
x4 Fast Page Mode DRAM

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中文翻译

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UD61464DC08 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP18,.3针数：18
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.81
访问模式：FAST PAGE最长访问时间：80 ns
I/O 类型：COMMONJESD-30 代码：R-PDIP-T18
长度：23.4 mm内存密度：262144 bit
内存集成电路类型：FAST PAGE DRAM内存宽度：4
功能数量：1端口数量：1
端子数量：18字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX4输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP18,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified刷新周期：256
座面最大高度：5.1 mm最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.06 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

UD61464DC08 数据手册

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Maintenance only  
UD61464  
64K x 4 DRAM  
Features  
FPM facilitates faster data operation Data Output Control  
with predefined row address. Via 8  
address inputs the 16 address bits  
are transmitted into the internal  
address memories in a time-multi-  
plex operation. The falling RAS-  
edge takes over the row address.  
After the row address hold time the  
column address can be applied. The  
bit pattern that is available at the  
address outputs during the set-up  
time and after the falling edge of  
CAS is interpreted as row address.  
During Write the column address is  
taken over with the falling edge of  
the control signal CAS, or W, whi-  
chever becomes active as the last.  
The selection of one or more  
memory circuits can be made via the  
RAS input.  
The usual state of the data output is  
the High-Z state. Whenever CAS is  
inactive (HIGH), Q will float (High-Z).  
Thus, CAS functions as data output  
control.  
After access time, in case of a Read  
cycle, the output is activated, and it  
contains the logic „0“ or „1“.  
Dynamic random access memory  
65536 x 4 bits manufactured  
using a CMOS technology  
RAS access times 70 ns/80 ns  
TTL-compatible  
Three-state outputs bidirectional  
256 refresh cycles  
4 ms refresh cycle time  
FAST PAGE MODE  
Operating modes: Read, Write,  
Read - Write,  
RAS only Refresh,  
Hidden Refresh with address  
transfer  
If the memory cycle is a Read,  
Read-Write or a Write cycle (W-con-  
trolled), Q changes from High-Z  
state to the active state („0“ or „1“).  
After access time, the contents of  
the selected cell will be available,  
with the exception of the Write cycle.  
The output remains active until CAS  
becomes inactive, irrespective of  
RAS becoming inactive or not. The  
memory cycle being a Write cycle  
(CAS-controlled), the data output  
keeps its High-Z state throughout  
Low power dissipation  
Power supply voltage 5 V  
Package PDIP18 (300 mil)  
Operating temperature range  
0 to 70 °C  
Quality assessment according to Read-Write-Control  
CECC 90000, CECC 90100 and The choice between Read or Write the whole cycle. This configuration  
CECC 90112  
cycle is made at the W input. HIGH makes Q fully controllable by the  
at the W input causes a Read cycle, user merely through the timing of W.  
meanwhile LOW leads to a Write Through storaging the data on out-  
Description  
cycle.  
put, they remain valid from the end  
Addressing  
Both CAS-controlled and W-control- of access time until the start of  
The UD61464 is a dynamic random led Write cycles are possible with another cycle.  
access memory organized 65536 activated RAS signal.  
words by 4 bits.  
Pin Configuration  
Pin Description  
Signal Name Signal Description  
1
VSS  
DQ3  
CAS  
DQ2  
A6  
18  
17  
16  
15  
14  
13  
12  
11  
10  
(OE)  
(WE)  
G
DQ0  
DQ1  
W
A0 - A7  
Address Inputs  
2
3
4
5
6
7
8
9
DQ0 - DQ3  
Data In/Out  
Read, Write Control  
Row Address Strobe  
Output Enable  
W
RAS  
G
RAS  
A0  
PDIP  
A3  
VCC  
VSS  
CAS  
Power Supply Voltage  
Ground  
A4  
A2  
A5  
A1  
A7  
Column Address Strobe  
VCC  
Top View  
1
December 12, 1997  
1234567...14

中文翻译

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