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UD61256DC07 PDF预览

UD61256DC07

更新时间： 2024-02-02 07:55:56
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
13页 224K
描述
256K x 1 DRAM

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UD61256DC07 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.84
访问模式：FAST PAGE最长访问时间：70 ns
I/O 类型：SEPARATEJESD-30 代码：R-PDIP-T16
长度：19.44 mm内存密度：262144 bit
内存集成电路类型：FAST PAGE DRAM内存宽度：1
功能数量：1端口数量：1
端子数量：16字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX1输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified刷新周期：256
座面最大高度：5.1 mm子类别：DRAMs
最大压摆率：0.07 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mm

UD61256DC07 数据手册

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Maintenance only  
UD61256  
256K x 1 DRAM  
Data Output Control  
Features  
Description  
The usual state of the data output is  
the High-Z state. Whenever CAS is  
Dynamic random access memory Addressing  
262144 x 1 bit manufactured  
using a CMOS technology  
RAS access times 70 ns, 80 ns  
TTL-compatible  
Three-state output  
256 refresh cycles  
The UD61256 is a dynamic Write- inactive (HIGH), Q will float (High-Z).  
Read-memory with random access. Thus, CAS functions as data output  
FPM facilitates faster data operation control.  
with predefined row address. Via 9 After access time, in case of a Read  
address inputs the 18 address bits cycle, the output is activated, and it  
are transmitted into the internal contains the logic „0“ or „1“.  
address memories in a time-multi- Q is then valid until CAS returns into  
plex operation. The falling RAS- to inactive state (HIGH).  
4 ms refresh cycle time  
FAST PAGE MODE  
Operating modes: Read, Write,  
Read - Write,  
edge takes over the row address. The memory cycle being a Read,  
During RAS Low, the column Read-Write or a Write cycle (W-con-  
RAS only Refresh,  
address together with the CAS trolled), Q changes from High-Z  
Hidden Refresh with address  
transfer  
Power Supply Voltage 5 V  
signal are taken over. The selection state to the active state („0“ or „1“).  
of one or more memory circuits can After the access time the contents of  
be made by activation of the RAS the selected cell is available, except  
Packages PDIP16 (300 mil) input.  
SOJ20/26 (300 mil)  
for the Write cycle.  
The output remains active until CAS  
Operating temperature range  
0 to 70 °C  
Read-Write-Control  
The choice between Read or Write RAS becoming inactive or not. The  
becomes inactive, irrespective of  
Quality assessment according to cycle is made at the W input. HIGH memory cycle being a Write cycle  
CECC 90000, CECC 90100 and at the W input causes a Read cycle, (CAS-controlled), the data output  
CECC 90112  
meanwhile LOW leads to a Write keeps its High-Z state throughout  
cycle. the whole cycle. This configuration  
Both CAS-controlled and W-control- makes Q fully controllable by the  
led Write cycles are possible with user merely through the timing of W.  
activated RAS signal.  
The output storaging the data, they  
remain valid from the end of access  
time until the start of another cycle.  
Pin Description  
Pin Configuration  
Signal Name Signal Description  
1
2
3
4
5
V
26  
25  
24  
23  
22  
A8  
D
VSS  
1
2
3
4
5
6
7
8
A8  
D
16  
15  
14  
13  
12  
11  
10  
9
A0 - A8  
D
Address Inputs  
Data Input  
CAS  
Q
CAS  
Q
W
Read, Write Control  
Row Address Strobe  
Power Supply Voltage  
Ground  
W
W
A6  
n.c.  
RAS  
n.c.  
RAS  
UCC  
USS  
CAS  
Q
A6  
A3  
A4  
A5  
A7  
RAS  
PDIP  
A0  
A2  
Column Address Strobe  
Data Output  
SOJ  
A1  
n.c.  
no connected  
VCC  
n.c.  
A0  
9
18  
17  
16  
15  
14  
n.c.  
A3  
A4  
A5  
A7  
10  
11  
12  
13  
Top View  
A2  
A1  
VCC  
Top View  
December 12, 1997  
1
1234567...13

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