UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
Complementary Switch FET Drivers
Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715
1
FEATURES
DESCRIPTION
These two families of high speed drivers are
designed to provide drive waveforms for
•
•
Single Input (PWM and TTL Compatible)
High-Current Power FET Driver, 1-A Source
and 2-A Sink
complementary switches. Complementary switch
configurations are commonly used in synchronous
rectification circuits and active clamp/reset circuits,
which provide zero voltage switching. In order to
facilitate the soft switching transitions, independently
programmable delays between the two output
waveforms are provided on these drivers. The delay
pins also have true-zero voltage-sensing capability
•
•
Auxiliary Output FET Driver, 0.5-A Source and
1-A Sink
Time Delays Between Power and Auxiliary
Outputs Independently Programmable from 50
to 500-ns
•
Time Delay or True Zero-Voltage Operation
Independently Configurable for Each Output
which
allows
immediate
activation
of
the
corresponding switch when zero voltage is applied.
These devices require a PWM-type input to operate
and interface with commonly available PWM
controllers.
•
•
•
•
•
Switching Frequency to 1 MHz
Typical 50-ns Propagation Delays
ENBL Pin Activates 220-μA Sleep Mode
Power Output is Active-Low in Sleep Mode
Synchronous Rectifier Driver
In the UC1714 series, the AUX output is inverted to
allow driving a p-channel MOSFET. In the UC1715
series, the two outputs are configured in a true
complementary fashion.
BLOCK DIAGRAM
2
PWR
50ns œ500ns
TIMER
INPUT
T1
6
7
S
Q
R
UC1714
ONLY
VREF
4
1
AUX
VCC
50ns œ500ns
TIMER
S
Q
VCC
BIAS
ENBL
GND
5V
LOGIC
GATES
T2
5
R
VREF
TIMER
REF
3V
3
GND
1.4V
ENBL
8
ENABLE
Pin numbers refer to J, N and D packages.
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