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UC1715J883B PDF预览

UC1715J883B

更新时间： 2024-09-26 12:01:59
品牌 Logo 应用领域
德州仪器 - TI 驱动器开关
页数 文件大小 规格书
16页 773K
描述
Complementary Switch FET Drivers

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UC1715J883B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP8,.3针数：8
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.88
驱动器位数：2高边驱动器：YES
接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVERJESD-30 代码：R-GDIP-T8
长度：9.81 mm功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-55 °C最大输出电流：0.2 A
标称输出峰值电流：2 A封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：5.08 mm子类别：Peripheral Drivers
最大供电电压：20 V最小供电电压：7 V
标称供电电压：15 V表面贴装：NO
技术：BIPOLAR温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
断开时间：0.1 µs接通时间：0.1 µs
宽度：7.62 mmBase Number Matches：1

UC1715J883B 数据手册

 浏览型号UC1715J883B的Datasheet PDF文件第2页浏览型号UC1715J883B的Datasheet PDF文件第3页浏览型号UC1715J883B的Datasheet PDF文件第4页浏览型号UC1715J883B的Datasheet PDF文件第5页浏览型号UC1715J883B的Datasheet PDF文件第6页浏览型号UC1715J883B的Datasheet PDF文件第7页 
UC1714, UC1715, UC2714  
UC2715, UC3714, UC3715  
www.ti.com  
SLUS170B –FEBRUARY 1999–REVISED MAY 2013  
Complementary Switch FET Drivers  
Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715  
1
FEATURES  
DESCRIPTION  
These two families of high speed drivers are  
designed to provide drive waveforms for  
•
•
Single Input (PWM and TTL Compatible)  
High-Current Power FET Driver, 1-A Source  
and 2-A Sink  
complementary switches. Complementary switch  
configurations are commonly used in synchronous  
rectification circuits and active clamp/reset circuits,  
which provide zero voltage switching. In order to  
facilitate the soft switching transitions, independently  
programmable delays between the two output  
waveforms are provided on these drivers. The delay  
pins also have true-zero voltage-sensing capability  
•
•
Auxiliary Output FET Driver, 0.5-A Source and  
1-A Sink  
Time Delays Between Power and Auxiliary  
Outputs Independently Programmable from 50  
to 500-ns  
•
Time Delay or True Zero-Voltage Operation  
Independently Configurable for Each Output  
which  
allows  
immediate  
activation  
of  
the  
corresponding switch when zero voltage is applied.  
These devices require a PWM-type input to operate  
and interface with commonly available PWM  
controllers.  
•
•
•
•
•
Switching Frequency to 1 MHz  
Typical 50-ns Propagation Delays  
ENBL Pin Activates 220-μA Sleep Mode  
Power Output is Active-Low in Sleep Mode  
Synchronous Rectifier Driver  
In the UC1714 series, the AUX output is inverted to  
allow driving a p-channel MOSFET. In the UC1715  
series, the two outputs are configured in a true  
complementary fashion.  
BLOCK DIAGRAM  
2
PWR  
50ns œ500ns  
TIMER  
INPUT  
T1  
6
7
S
Q
R
UC1714  
ONLY  
VREF  
4
1
AUX  
VCC  
50ns œ500ns  
TIMER  
S
Q
VCC  
BIAS  
ENBL  
GND  
5V  
LOGIC  
GATES  
T2  
5
R
VREF  
TIMER  
REF  
3V  
3
GND  
1.4V  
ENBL  
8
ENABLE  
Pin numbers refer to J, N and D packages.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2013, Texas Instruments Incorporated  
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