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UC1714N PDF预览

UC1714N

更新时间: 2024-09-26 12:59:35
品牌 Logo 应用领域
德州仪器 - TI 驱动器开关
页数 文件大小 规格书
8页 276K
描述
2A BUF OR INV BASED MOSFET DRIVER, PDIP8

UC1714N 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
高边驱动器:NO接口集成电路类型:BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码:R-PDIP-T8长度:9.78 mm
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
标称输出峰值电流:2 A封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:5.33 mm最大供电电压:20 V
最小供电电压:7 V标称供电电压:15 V
表面贴装:NO温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL断开时间:0.1 µs
接通时间:0.1 µs宽度:7.62 mm
Base Number Matches:1

UC1714N 数据手册

 浏览型号UC1714N的Datasheet PDF文件第2页浏览型号UC1714N的Datasheet PDF文件第3页浏览型号UC1714N的Datasheet PDF文件第4页浏览型号UC1714N的Datasheet PDF文件第5页浏览型号UC1714N的Datasheet PDF文件第6页浏览型号UC1714N的Datasheet PDF文件第7页 
UC1714/5  
UC2714/5  
UC3714/5  
Complementary Switch FET Drivers  
FEATURES  
DESCRIPTION  
Single Input (PWM and TTL  
Compatible)  
These two families of high speed drivers are designed to provide drive  
waveforms for complementary switches. Complementary switch configura-  
tions are commonly used in synchronous rectification circuits and active  
clamp/reset circuits, which can provide zero voltage switching. In order to  
facilitate the soft switching transitions, independently programmable de-  
lays between the two output waveforms are provided on these drivers.  
The delay pins also have true zero voltage sensing capability which allows  
immediate activation of the corresponding switch when zero voltage is ap-  
plied. These devices require a PWM-type input to operate and can be in-  
terfaced with commonly available PWM controllers.  
High Current Power FET Driver, 1.0A  
Source/2A Sink  
Auxiliary Output FET Driver, 0.5A  
Source/1A Sink  
Time Delays Between Power and  
Auxiliary Outputs Independently  
Programmable from 50ns to 500ns  
In the UC1714 series, the AUX output is inverted to allow driving a  
p-channel MOSFET. In the UC1715 series, the two outputs are configured  
in a true complementary fashion.  
Time Delay or True Zero-Voltage  
Operation Independently Configurable  
for Each Output  
Switching Frequency to 1MHz  
Typical 50ns Propagation Delays  
ENBL Pin Activates 220µA Sleep  
Mode  
Power Output is Active Low in Sleep  
Mode  
Synchronous Rectifier Driver  
BLOCK DIAGRAM  
2
PWR  
50ns –500ns  
TIMER  
INPUT  
T1  
6
7
S
Q
R
UC1714  
ONLY  
V
REF  
4
1
AUX  
VCC  
50ns –500ns  
TIMER  
S
Q
V
5V  
BIAS  
ENBL  
LOGIC  
GATES  
CC  
T2  
5
R
V
REF  
TIMER  
REF  
3V  
GND  
3
GND  
1.4V  
ENBL  
8
ENABLE  
Note: Pin numbers refer to J, N and D packages.  
UDG-99028  
02/99  

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