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TSB83AA23ZAY PDF预览

TSB83AA23ZAY

更新时间： 2024-11-25 03:09:27
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC时钟
页数 文件大小 规格书
8页 145K
描述
IEEE Std 1394b-2002 PHY AND OHCI LINK DEVICE

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TSB83AA23ZAY 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：LFBGA, BGA167,14X14,32针数：167
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01Factory Lead Time：12 weeks
风险等级：1.7边界扫描：YES
总线兼容性：PCI最大时钟频率：33 MHz
通信协议：IEEE1394最大数据传输速率：100 MBps
JESD-30 代码：S-PBGA-B167JESD-609代码：e1
长度：12 mm低功率模式：NO
湿度敏感等级：3端子数量：167
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA167,14X14,32封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.9,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm子类别：Bus Controllers
最大压摆率：120 mA表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

TSB83AA23ZAY 数据手册

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TSB83AA23  
www.ti.com  
www.ti.com  
SLLS787–AUGUST 2007  
IEEE Std 1394b-2002 PHY AND OHCI LINK DEVICE  
1
FEATURES  
23  
•
Fully Supports Provisions of IEEE Std  
1394b-2002 Revision 1.33+ at 1-Gigabit  
Signaling Rates  
•
Fail-Safe Circuitry Senses Sudden Loss of  
Power to the Device and Disables Ports to  
Ensure That TSB83AA23 Does Not Load  
TPBIAS of Any Connected Device and Blocks  
Any Leakage From the Port Back to Power  
Plane  
•
Fully Supports Provisions of IEEE Std  
1394a-2000 and IEEE Std 1394-1995 for  
High-Performance Serial Bus  
•
•
IEEE Std 1394a-2000-Compliant  
Common-Mode Noise Filter on Incoming Bias  
Detect Circuit to Filter Out Crosstalk Noise  
•
•
Fully Interoperable With Firewire™, i.LINK™,  
and SB1394 Implementations of IEEE Std 1394  
Provides Three Fully Backward-Compatible,  
(IEEE Std 1394a-2000 Fully Compliant)  
Bilingual IEEE Std 1394b-2002 Cable Ports at  
up to 800 Megabits per Second (Mbps)  
Port Programmable to Force IEEE Std  
1394a-2000 Mode to Allow Use of IEEE Std  
1394a-2000 Connectors (IEEE Std 1394b-2002  
Signaling Must Not Be Put Across IEEE Std  
1394a-2000 Connectors or Cables)  
•
Full IEEE Std 1394a-2000 Support Includes:  
–
–
–
–
–
–
Connection Debounce  
Arbitrated Short Reset  
Multispeed Concatenation  
Arbitration Acceleration  
Fly-By Concatenation  
•
•
3.3-V and 5-V PCI Signaling Environments  
Serial-Bus Data Rates of 100 Mbps, 200 Mbps,  
400 Mbps, and 800 Mbps  
•
•
Physical Write Posting of up to Three  
Outstanding Transactions  
Port Disable/Suspend/Resume  
Serial ROM or Boot ROM Interface Supports  
2-Wire Serial EEPROM Devices  
•
•
Extended Resume Signaling for Compatibility  
With Legacy Digital Video (DV) Devices  
•
•
33-MHz/32-Bit PCI Interface  
Power-Down Features to Conserve Energy in  
Battery-Powered Applications  
Multifunction Terminal (MFUNC Terminal 1):  
–
PCI_CLKRUN Protocol Per PCI Mobile  
•
•
Low-Power Sleep Mode  
Design Guide  
Fully Compliant With Open Host Controller  
Interface (OHCI) Requirements  
–
–
General-Purpose I/O (GPIO)  
CYCLEIN/CYCLEOUT for External Cycle  
Timer Control for Customized  
Synchronization  
•
•
Cable Power Presence Monitoring  
Cable Ports Monitor Line Conditions for Active  
Connection to Remote Node  
•
•
PCI Burst Transfers and Deep FIFOs to  
Tolerate Large Host Latency  
•
Register Bits Give Software Control of  
Contender Bit, Power-Class Bits, Link Active  
Control Bit, and IEEE Std 1394a-2000 Features  
–
–
–
–
Transmit FIFO—5K Asynchronous  
Transmit FIFO—2K Isochronous  
Receive FIFO—2K Asynchronous  
Receive FIFO—2K Isochronous  
•
•
Interoperable With Other 1394 Physical Layers  
(PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies  
Low-Jitter, External Crystal Oscillator Provides  
Transmit and Receive Data at 100/200/400/800  
Mbps and Link-Layer Controller (LLC) Clock at  
49.152 MHz and 98.304 MHz  
D0, D1, D2, and D3 Power States and PME  
Events Per PCI Bus Power Management  
Interface Specification  
•
•
Programmable Asynchronous Transmit  
Threshold  
•
•
Separate Bias (TPBIAS) for Each Port  
Software Device Reset (SWR)  
Isochronous Receive Dual-Buffer Mode  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
Firewire is a trademark of Apple Computer, Inc.  
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.  
Copyright © 2007, Texas Instruments Incorporated  
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