Datasheet > TS88915T

TS88915T

更新时间： 2024-11-09 23:37:55

品牌	Logo	应用领域
其他 - ETC		时钟驱动器
页数	文件大小	规格书
19页	322K
描述
TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions

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中文翻译

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TS88915T 数据手册

Features

• Vcc = 5V ± 5%

• Military Temperature Range

• Fully Compatible with the TS68040

• Five Low Skew Outputs

– Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End

Frequency Locked to the SYNC Input

• Three Additional Outputs are Available:

– The 2X_Q Output Runs Twice the System “Q” Frequency

– The Q/2 Output Runs At 1/2 the System “Q” Frequency

– The Q5 Output is Inverted (180° Phase Shift)

• Two Selectable Clock Inputs

– Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes

– Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

– All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes

• Input Frequency Range From 5 MHz to 2X_Q FMAX

• Three Input/Output Ratios

Low Skew

CMOS PLL

Clock Driver

Tri-State 70 and

100 MHz

– Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available

• Low Part-to-part Skew

– The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is

Less than 550 ps (Derived From the tPD Specification, which Defines the

Part-to-part Skew)

Versions

• CMOS and TTL Compatible

– All Outputs Can Drive Either CMOS or TTL Inputs

– All Inputs are TTL-level Compatible

• LOCK Indicator (LOCK) Indicates a Phase-locked State

TS88915T

Description

The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its

low skew outputs’ frequency and phase onto an input reference clock. It is designed to

provide clock distribution for high performance microprocessors such as TS68040,

TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.

Screening/Quality

This Product is Manufactured:

•

Based Upon the Generic Flow of MIL-STD-883

or According to Atmel-Grenoble Standard

R suffix

PGA 29

W suffix

LDCC 28

Ceramic Pin Grid Array

Leaded Ceramic Chip Carrier

Rev. 2122A–HIREL–06/02

12 3 4 5 6 7...19

中文翻译

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与TS88915T相关器件

型号	品牌	获取价格	描述	数据表
TS88915TCRD/T100	ATMEL	获取价格	PLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TCRD/T70	ATMEL	获取价格	PLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMR70	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMRB/T70	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMRD/T70	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMW100	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMW70	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMWB/T70	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMWD/T100	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TVR100	ATMEL	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA

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