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TS88915TMR70 PDF预览

TS88915TMR70

更新时间: 2024-11-08 15:55:07
品牌 Logo 应用领域
爱特美尔 - ATMEL ATM异步传输模式驱动逻辑集成电路
页数 文件大小 规格书
19页 258K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA-29

TS88915TMR70 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:PGA包装说明:PGA, PGA29,6X6
针数:29Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.05
输入调节:MUXJESD-30 代码:S-CPGA-P29
JESD-609代码:e0长度:15.24 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.036 A
功能数量:1反相输出次数:
端子数量:29实输出次数:8
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA29,6X6
封装形状:SQUARE封装形式:GRID ARRAY
电源:5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.75 ns座面最大高度:4.117 mm
子类别:Clock Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR宽度:15.24 mm
最小 fmax:70 MHzBase Number Matches:1

TS88915TMR70 数据手册

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Features  
Vcc = 5V ± 5%  
Military Temperature Range  
Fully Compatible with the TS68040  
Five Low Skew Outputs  
– Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End  
Frequency Locked to the SYNC Input  
Three Additional Outputs are Available:  
– The 2X_Q Output Runs Twice the System “Q” Frequency  
– The Q/2 Output Runs At 1/2 the System “Q” Frequency  
– The Q5 Output is Inverted (180° Phase Shift)  
Two Selectable Clock Inputs  
– Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes  
– Test Mode Pin (PLL_EN) Provided for Low Frequency Testing  
– All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes  
Input Frequency Range From 5 MHz to 2X_Q FMAX  
Three Input/Output Ratios  
Low Skew  
CMOS PLL  
Clock Driver  
Tri-State 70 and  
100 MHz  
– Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available  
Low Part-to-part Skew  
– The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is  
Less than 550 ps (Derived From the tPD Specification, which Defines the  
Part-to-part Skew)  
Versions  
CMOS and TTL Compatible  
– All Outputs Can Drive Either CMOS or TTL Inputs  
– All Inputs are TTL-level Compatible  
LOCK Indicator (LOCK) Indicates a Phase-locked State  
TS88915T  
Description  
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its  
low skew outputs’ frequency and phase onto an input reference clock. It is designed to  
provide clock distribution for high performance microprocessors such as TS68040,  
TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.  
Screening/Quality  
This Product is Manufactured:  
Based Upon the Generic Flow of MIL-STD-883  
or According to Atmel-Grenoble Standard  
R suffix  
PGA 29  
W suffix  
LDCC 28  
Ceramic Pin Grid Array  
Leaded Ceramic Chip Carrier  
Rev. 2122A–HIREL–06/02  

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