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TS88915TCRD/T70 PDF预览

TS88915TCRD/T70

更新时间： 2024-09-21 19:55:19
品牌 Logo 应用领域
爱特美尔 - ATMEL 驱动逻辑集成电路
页数 文件大小 规格书
20页 168K
描述
PLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA-29

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中文翻译

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TS88915TCRD/T70 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：PGA包装说明：PGA, PGA29,6X6
针数：29Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.05
输入调节：MUXJESD-30 代码：S-CPGA-P29
JESD-609代码：e0长度：15.24 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.036 A
功能数量：1反相输出次数：1
端子数量：29实输出次数：7
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：PGA封装等效代码：PGA29,6X6
封装形状：SQUARE封装形式：GRID ARRAY
电源：5 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.75 ns座面最大高度：4.117 mm
子类别：Clock Drivers最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR宽度：15.24 mm
最小 fmax：70 MHzBase Number Matches：1

TS88915TCRD/T70 数据手册

 浏览型号TS88915TCRD/T70的Datasheet PDF文件第2页浏览型号TS88915TCRD/T70的Datasheet PDF文件第3页浏览型号TS88915TCRD/T70的Datasheet PDF文件第4页浏览型号TS88915TCRD/T70的Datasheet PDF文件第5页浏览型号TS88915TCRD/T70的Datasheet PDF文件第6页浏览型号TS88915TCRD/T70的Datasheet PDF文件第7页 
TS88915T  
LOW SKEW CMOS PLL CLOCK DRIVER  
3-State 70 and 100 MHz Versions  
DESCRIPTION  
The TS88915T Clock Driver utilizes a phazed–locked loop  
(PLL) technology to lock its low skew outputs’ frequency and  
phase onto an input reference clock. It is designed to provide  
clock distribution for high performance microprocessors such  
as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge,  
RAM’s, MMU’s...  
MAIN FEATURES  
H Vcc = 5V ꢀ 5 %  
H MILITARY TEMPERATURE RANGE  
H TS68040 FULL COMPATIBLE  
H FIVE LOW SKEW OUTPUTS  
Five Outputs (Q0-Q4) with Output–to–Output skew < 500  
ps each being phase end frequency locked to the SYNC  
input.  
R Suffix  
PGA 29  
Ceramic Pin grid array  
H ADDITIONAL OUTPUTS  
Three additional outputs are available :  
– The 2X_Q output runs twice the system ”Q” frequency.  
– The Q/2 output runs at 1/2 the system ”Q” frequency.  
– The Q5 output is inverted (180° phase shift).  
H TWO SELECTABLE CLOCK INPUTS  
– Two selectable CLOCK inputs are available for test or  
redundancy purposes.  
– Test Mode pin (PLL_EN) provided for low frequency test-  
ing.  
– All outputs can go into high impedance (3-state) for board  
test purpose.  
H INPUT FREQUENCY RANGE FROM 5MHz to 2X_Q  
FMAX  
H THREE INPUT/OUTPUT RATIOS  
Input/Output phase–locked frequency ratios of 1:2, 1:1 and  
2:1 are available.  
H LOW PART-TO-PART SKEW  
The phase variation from part–to–part between the SYNC  
andFEEDBACKinputsislessthan550ps(derivedfromthe  
W suffix  
LDCC 28  
Leaded Ceramic Chip Carrier  
tPD specification, which defines the part-to-part skew).  
H CMOS AND TTL COMPATIBLE  
– All outputs can drive either CMOS or TTL inputs.  
– All inputs are TTL-level compatible.  
H LOCK Indicator (LOCK) indicated a phase–locked  
state.  
SCREENING / QUALITY  
This product is manufactured :  
H based upon the generic flow of MIL–STD–883.  
H or according to TCS standard.  
April 1999  
1/20  
1234567...20

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与TS88915TCRD/T70相关器件

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TS88915TMR70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMRB/T70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMRD/T70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TMW100 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMW70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMWB/T70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TMWD/T100 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC
TS88915TVR100 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TVR70 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA
TS88915TVW100 ATMEL

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, CQCC28, CERAMIC, LCC

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