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TS87C52X2-LCJD PDF预览

TS87C52X2-LCJD

更新时间： 2024-09-20 20:13:27
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器微控制器
页数 文件大小 规格书
56页 390K
描述
Microcontroller, 8-Bit, UVPROM, 8051 CPU, 40MHz, CMOS, CDIP40,

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中文翻译

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TS87C52X2-LCJD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP40,.6Reach Compliance Code：unknown
风险等级：5.92位大小：8
CPU系列：8051JESD-30 代码：R-XDIP-T40
JESD-609代码：e0端子数量：40
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP40,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：3/5 V
认证状态：Not QualifiedRAM（字节）：256
ROM（单词）：8192ROM可编程性：UVPROM
速度：40 MHz子类别：Microcontrollers
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

TS87C52X2-LCJD 数据手册

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TS80C32X2  
TS87C52X2  
TS80C52X2  
8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless  
1. Description  
TS80C52X2 is high performance CMOS ROM, OTP, The fully static design of the TS80C52X2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
EPROM and ROMless versions of the 80C51 CMOS  
single chip 8-bit microcontroller.  
The TS80C52X2 retains all features of the 80C51 with  
extended ROM/EPROM capacity (8 Kbytes), 256 bytes  
of internal RAM, a 6-source , 4-level interrupt system,  
an on-chip oscilator and three timer/counters.  
The TS80C52X2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
In addition, the TS80C52X2 has a dual data pointer, a  
more versatile serial channel that facilitates  
multiprocessor communication (EUART) and a X2 speed  
improvement mechanism.  
2. Features  
● 80C52 Compatible  
● Interrupt Structure with  
•
•
•
•
8051 pin and instruction compatible  
Four 8-bit I/O ports  
•
•
6 Interrupt sources,  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
● Full duplex Enhanced UART  
•
•
Framing error detection  
Automatic address recognition  
● High-Speed Architecture  
•
•
40 MHz @ 5V, 30MHz @ 3V  
● Low EMI (inhibit ALE)  
● Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
•
•
•
Idle mode  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
Power-down mode  
Power-off Flag  
● Dual Data Pointer  
● Once mode (On-chip Emulation)  
● Power supply: 4.5-5.5V, 2.7-5.5V  
● On-chip ROM/EPROM (8Kbytes)  
● Programmable Clock Out and Up/Down Timer/  
● Temperature ranges: Commercial (0 to 70oC) and  
Counter 2  
Industrial (-40 to 85oC)  
● Asynchronous port reset  
● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1  
(13.9 footprint), CQPJ44 (window), CDIL40  
(window)  
Rev.D - 16 November, 2000  
1
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