TRF1121
TRF1221
www.ti.com
SLWS170A–APRIL 2005–REVISED DECEMBER 2005
Dual VCO/PLL Synthesizer With IF Up-Converter
The TRF1121/TRF1221 are designed to function as
part of complete 2.5-GHz and 3.5-GHz radio chipsets,
respectively. In the chipset, the transmit chain
operates as a double up converter from an IF
frequency input (typically from a baseband modem's
DAC) to an RF output frequency. The TRF1121/
TRF1221 performs the first up conversion from IF
signals in the range of 10 MHz to 60 MHz to a
second IF frequency in the range of 300 MHz to 360
MHz. The radio chipset features sufficient linearity,
phase noise, and dynamic range to work in either
single carrier or multi-carrier, line-of-sight or
non-line-of-sight, standard (IEEE 802.16), or
proprietary systems. Due to the modular nature of the
chipset, it is ideal for use in systems that employ
transmit or receive diversity.
FEATURES
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•
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Low Phase Noise
Image Reject Upconverter
Dual VCO/PLL For Double Up Conversion
Architecture
•
On-Chip VCO, Resonator and PLL Only
Requires Off-Chip Loop Filter
•
•
External S-Band VCO Option
5-Bit Transmit Level Control, 32 dB in 1 dB
Steps
SPECIFICATIONS
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S-Band LO Frequency Range:
– TRF1121: 1500 to 2500 MHz
– TRF1221: 1700 to 3600 MHz
LPCC−48 PACKAGE
(TOP VIEW)
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•
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UHF LO Frequency Range: 250 to 350 MHz
Input Frequency Range: 10 MHz to 70 MHz
S-Band LO Phase Noise Typical 0.5 rms (100
Hz to 1 MHz)
•
•
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Output Power Range From –32 dBm to 0 dBm
in 1 dB Steps (500-mVpp Diff Input)
Minimum UHF LO Step Size of 50 kHz For
TRF1121 and 62.5 kHz for TRF1221
Image Rejection: –50 dBc, Typical (20–40 MHz
Tx IF Input)
36
35
34
33
32
31
30
29
28
27
26
25
1
CP2O
LD2
EXTLO2IP
EXTLO2IN
TXON
2
3
LF2
4
DATA
CLK
IFOP
5
VCCIF
IFON
6
VCCD2
FR
•
•
LO Leakage: –36 dBm, Typical
3rd Order IMD: < –60 dBc In Max Gain
7
GND
8
VCCD1
FRBP
EN
GND
9
GAIN[4]
GAIN[3]
GAIN[2]
GAIN[1]
10
11
12
DESCRIPTION
LF1
LD1
The TRF1121/TRF1221 are VHF-UHF upconverters
with integrated UHF and S-band frequency
synthesizers for radio applications in the 2GHz to 4
GHz range. The IC performs the first up-conversion
and generates the local oscillator (LO) for the second
up-conversion. The device uniquely integrates an
image reject mixer, IF gain blocks, 5-bit gain control,
and two complete phase locked loop (PLL) circuits
including: VCOs, resonator circuit, varactors, dividers,
and phase detectors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.