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TRF1221IRGZT PDF预览

TRF1221IRGZT

更新时间： 2024-01-12 16:58:03
品牌 Logo 应用领域
德州仪器 - TI 射频和微波射频上变频器射频下变频器微波上变频器微波下变频器
页数 文件大小 规格书
26页 1237K
描述
1700MHz - 3600MHz RF/MICROWAVE UP CONVERTER, 0dBm OUTPUT POWER-MAX, GREEN, PLASTIC, MO-220, LPCC, QFN-48

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TRF1221IRGZT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：LCC48,.27SQ,20
Reach Compliance Code：compliantFactory Lead Time：1 week
风险等级：5.8构造：COMPONENT
最大中频频率：350 MHz最小中频频率：250 MHz
输入功率最小值（CW）：20 dBmJESD-609代码：e3
LO 可调谐：YES安装特点：SURFACE MOUNT
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C最大输出功率：
封装主体材料：PLASTIC/EPOXY封装等效代码：LCC48,.27SQ,20
电源：5 VRF输出最大频率：3600 MHz
RF输出频率-最小值：1700 MHz射频/微波设备类型：UP CONVERTER
子类别：RF/Microwave Up/Down Converters表面贴装：YES
端子面层：Matte Tin (Sn)Base Number Matches：1

TRF1221IRGZT 数据手册

 浏览型号TRF1221IRGZT的Datasheet PDF文件第1页浏览型号TRF1221IRGZT的Datasheet PDF文件第2页浏览型号TRF1221IRGZT的Datasheet PDF文件第4页浏览型号TRF1221IRGZT的Datasheet PDF文件第5页浏览型号TRF1221IRGZT的Datasheet PDF文件第6页浏览型号TRF1221IRGZT的Datasheet PDF文件第7页 
TRF1121  
TRF1221  
www.ti.com  
SLWS170A–APRIL 2005–REVISED DECEMBER 2005  
TERMINAL FUNCTIONS  
TERMINAL  
NAME  
CP2O  
I/O  
TYPE  
DESCRIPTION  
NO.  
1
O
O
O
I
Analog Synthesizer 2 charge pump output  
2
LD2  
Digital Synthesizer 2 lock detect output, High is locked.  
Analog Lock detect filter capacitor for LO2, 0.01 µF typical 100 kΩ pull-up(1)  
Digital Serial interface data input  
3
LF2  
4
DATA  
CLK  
5
I
Digital Serial interface clock input  
6
VCCD2  
FR  
I
Power +5 V power for digital  
7
I
Analog 18-MHz reference clock input, HCMOS input. (DC level = 2.5 V)  
Power +5 V power for digital  
8
VCCD1  
FRBP  
EN  
I
9
O
I
Analog Reference frequency bypass. Internally biased to 2.5 V.  
Digital Serial interface load enable (active high)  
Analog Lock detect filter capacitor for LO1, 0.01 µF typical 100 kΩ(1)  
Digital Synthesizer 1 lock detect output, High is locked.  
Analog Synthesizer 1 charge pump output  
10  
11  
12  
13  
14  
LF1  
O
O
O
O
LD1  
CP1O  
LO1BPA  
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to  
any other pin.  
15  
16  
17  
LO1TUN  
LO1BPB  
VCCLO1  
I
O
I
Analog VCO synthesizer 1 tuning port  
Analog Bypass capacitor for LO1 0.1 µF (min) DCV =1.0 V  
Power VCC for LO1  
18, 19, 20, 29, GND  
30, 37, 39, 42  
Power Ground  
21  
22  
23  
24  
25  
26  
27  
28  
31  
32  
33  
34  
35  
36  
38  
40  
41  
43  
BBIN  
I
I
Analog Baseband IF input (2 kΩ diff) negative, dc-coupled, Internal voltage is 4 V DC  
Analog Baseband IF input (2 kΩ diff) positive, dc-coupled, Internal voltage is 4 V DC  
Power +5V power Analog  
BBIP  
VCCUPC  
GAIN[0]  
GAIN[1]  
GAIN[2]  
GAIN[3]  
GAIN[4]  
IFON  
I
I
Digital Gain control bit 0 (LSB) – Logic low induces 1-dB attenuation  
Digital Gain control bit 1 – Logic low induces 2-dB attenuation  
Digital Gain control bit 2 – Logic low induces 4-dB attenuation  
Digital Gain control bit 3 – Logic low induces 8-dB attenuation  
Digital Gain control bit 4 (MSB) – Logic low induces 16-dB attenuation  
Analog IF analog output (100 Ω diff ) negative, dc-coupled, Internal voltage is 2.1 V DC  
Power +5 V power Analog  
I
I
I
I
O
I
VCCIF  
IFOP  
O
I
Analog IF analog output (100 Ω diff ) positive, dc-coupled, Internal voltage is 2.1 V DC  
Digital IF amplifier enable active high  
TXON  
EXTLO2IN  
EXTLO2IP  
VCCLO2  
LO2ON  
LO2OP  
LO2BBPA  
I
Analog External input for LO2 (differential) negative and logic level for VCO select.  
Analog External input for LO2 (differential) positive and logic level for VCO select.  
Power VCC for LO2 A and B  
I
I
O
O
O
Analog LO2 output (differential) Negative and positive VCC bias (+5 V) for LO buffer amp.  
Analog LO2 output (differential) Positive and positive VCC bias (+5 V) for LO buffer amp.  
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to  
any other pin.  
44  
45  
46  
LO2BTUN  
LO2BBPB  
LO2ABPA  
I
Analog LO2B Tune Port  
O
O
Analog Bypass cap. for LO2B 0.1 µF (min) DCV = 1 V  
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to  
any other pin.  
47  
48  
LO2ATUN  
LO2ABPB  
I
Analog LO2A tune port  
O
Analog Bypass capacitor for LO2A 0.1 µF (min ) DCV = 1 V  
Back  
Back side of package has metal base that must be grounded for thermal and RF performance  
(1) Current leakage on the order of 10µA through the capacitor or by any other means from either LF pin can cause false loss of lock  
signals. The two pullup resistors (R16 and R17) in Figure 23 reduce this sensitivity.  
3
1234567...26

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