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TQ8101C

更新时间: 2024-09-18 22:19:15
品牌 Logo 应用领域
TRIQUINT /
页数 文件大小 规格书
14页 230K
描述
622/155 Mb/s SONET/SDH MDFP

TQ8101C 数据手册

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S E M I C O N D U C T O R , I N C .  
TQ8101C  
The TQ8101C is a SONET/SDH transceiver that integrates Multiplexing,  
Demultiplexing, SONET/SDH Framing, clock synthesis PLL (MDFP), and  
loopback functions in a single monolithic integrated circuit. Implementation  
with the TQ8101C requires only a simple external RC loop filter and standard  
TTL and ECL power supplies. For optimal performance, the TQ8101C MDFP  
is packaged in a 68-pin multilayer ceramic (MLC) surface-mount package  
with an integral CuW heat spreader. The TQ8101C provides an integrated  
solution for physical interfaces intended for use in STS-12/STM-4  
(622.08-Mb/s) and STS-3/STM-1 (155.52-Mb/s) SONET/SDH systems.  
622/155 Mb/s  
SONET/SDH MDFP  
Features  
• Byte-wide Multiplexing,  
Demultiplexing, Framing, and  
PLL (MDFP) in one device  
• Choice of STS-12/STM-4 or  
STS-3/STM-1 transmission rates  
The TQ8101C meets ANSI, Bellcore, and ITU requirements for a SONET/  
SDH device. With a 51.84-MHz reference clock, the phase-locked loop  
(PLL) provides 77.76-MHz or 19.44-MHz output for the multiplexer and  
77.76-MHz or 19.44-MHz and 51.84-MHz output for the demultiplexer.  
• Configurable master or slave  
reference clock generation and  
PLL bypass for external clocking  
Typical SONET/SDH system applications for the TQ8101C include:  
• 77.76 MHz or 19.44 MHz output  
for the multiplexer; 77.76 MHz or  
19.44 MHz and 51.84 MHz  
• Transmission system transport cards  
• Switch and cross-connect line cards  
• Repeaters  
• ATM physical layer interfaces  
• Test equipment  
output for the demultiplexer  
• External RC loop filter  
• Pass-through mode and three  
loopback modes for enhanced  
filed diagnostics  
• Add/drop multiplexers  
Figure 1. Logical Application  
• Frame-synchronous and byte-  
aligned demultiplexer output,  
compliant with SONET and SDH  
TQ8101C  
MDFP  
600  
PM5312  
STTX  
PM5355  
S/UNI-622  
0.68 µF  
or  
VEE  
• Search, detect, and recovery of  
framing on out-of-frame input  
MXDT(7:0)  
TOUT(7:0)  
8-bit data  
Driver  
and  
• Standard TTL and differential or  
single-ended ECL I/O (except TXCK)  
LASER  
DXDT(7:0)  
OOF  
RIN(7:0)  
8-bit data  
OOF fix*  
OC-3 or OC-12  
OOF  
O/E Rx +  
TQ8103  
CDR  
• Tristate TTL output for factory  
circuit-board testability  
MXCK0  
DXSYNC  
DXCK  
TCLK  
RIFP  
OC-3 or OC-12  
• 68-pin TriQuint MLC controlled-Z  
surface-mount package with  
integral heat spreader  
RICLK  
CNTL(3:0)  
51.84 MHz  
CMOS OSC  
Dual-supply operation (+5V, 5.2V)  
Low power dissipation (2.3W nom.)  
*Contact PMC-Sierra for  
application note.  
1
For additional information and latest specifications, see our website: www.triquint.com  

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