TPIC6596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS096 – APRIL 2000
DW OR N PACKAGE
(TOP VIEW)
Low r
. . . 1.3 Ω Typ
DS(on)
Avalanche Energy . . . 75 mJ
Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
PGND
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
V
LGND
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
1.5-A Pulsed Current Per Output
Output Clamp Voltage at 45 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
13 SRCK
12
11
RCK
description
PGND
PGND
The TPIC6596 is a monolithic, high-voltage, high-
current power 8-bit shift register designed for use
in systems that require relatively high load power.
The device contains a built-in voltage clamp on
the outputs for inductive transient protection.
Power driver applications include relays, sole-
noids, and other medium-current or high-voltage
loads.
†
logic symbol
9
EN3
G
12
RCK
C2
SRG8
8
R
SRCLR
SRCK
13
C1
4
5
3
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK) respectively. The storage register transfers
data to the output buffer when shift-register clear
(SRCLR) is high. When SRCLR is low, all
registers in the device are cleared. When output
enable (G) is held high, all data in the output
buffers is held low and all drain outputs are off.
When G is held low, data from the storage register
is transparent to the output buffers. The serial
output (SER OUT) is clocked out of the device on
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
1D
2
SER IN
6
7
14
15
16
17
18
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved
performance for applications where clock signals may be skewed, devices are not located near one another,
or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is
high, the DMOS-transistor outputs have sink current capability.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and20areinternallyconnected, andeachpinmustbeexternallyconnectedtothepowersystemgroundinorder
to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1,
10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between
the logic and load circuits.
The TPIC6596 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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