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TPIC6A595NE

更新时间： 2024-11-30 22:25:31
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
12页 179K
描述
POWER LOGIC 8-BIT SHIFT REGISTER

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TPIC6A595NE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：DIP-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.62Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：182724
Samacsys Pin Count：20Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Dual-In-Line PackagesSamacsys Footprint Name：N (R-PDIP-T20)
Samacsys Released Date：2018-02-06 00:08:03Is Samacsys：N
其他特性：PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT计数方向：RIGHT
系列：6AJESD-30 代码：R-PDIP-T20
JESD-609代码：e4长度：24.51 mm
负载电容（CL）：30 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED最大电源电流（ICC）：5 mA
传播延迟（tpd）：125 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.86 mmBase Number Matches：1

TPIC6A595NE 数据手册

 浏览型号TPIC6A595NE的Datasheet PDF文件第2页浏览型号TPIC6A595NE的Datasheet PDF文件第3页浏览型号TPIC6A595NE的Datasheet PDF文件第4页浏览型号TPIC6A595NE的Datasheet PDF文件第5页浏览型号TPIC6A595NE的Datasheet PDF文件第6页浏览型号TPIC6A595NE的Datasheet PDF文件第7页 
TPIC6A595  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS005A – APRIL 1993 – REVISED JANUARY 1995  
NE PACKAGE  
(TOP VIEW)  
Low r  
. . . 1 Ω Typ  
DS(on)  
Output Short-Circuit Protection  
Avalanche Energy . . . 75 mJ  
Eight 350-mA DMOS Outputs  
50-V Switching Capability  
Devices Are Cascadable  
DRAIN2  
DRAIN3  
SRCLR  
G
DRAIN1  
DRAN0  
SER IN  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
V
CC  
PGND  
PGND  
RCK  
PGND  
Low Power Consumption  
15 PGND  
14  
13  
12  
11  
LGND  
description  
SRCK  
DRAIN4  
DRAIN5  
SER OUT  
DRAIN7  
DRAIN6  
The TPIC6A595 is a monolithic, high-voltage,  
high-current power logic 8-bit shift register  
designed for use in systems that require relatively  
high load power. The device contains a built-in  
voltage clamp on the outputs for inductive  
transient protection. Power driver applications  
include relays, solenoids, and other medium-cur-  
rent or high-voltage loads. Each open-drain  
DMOS transistor features an independent  
chopping current-limiting circuit to prevent  
damage in the case of a short circuit.  
DW PACKAGE  
(TOP VIEW)  
DRAIN2  
DRAIN3  
SRCLR  
G
DRAIN1  
DRAIN0  
SER IN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
3
V
4
CC  
PGND  
PGND  
PGND  
PGND  
RCK  
PGND  
5
PGND  
6
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit, D-type storage  
register. Data transfers through both the shift and  
storage registers on the rising edge of the shift-  
register clock (SRCK) and the register clock  
(RCK), respectively. The storage register  
transfers data to the output buffer when shift-  
register clear (SRCLR) is high. When SRCLR is  
low, theinputshiftregisteriscleared. Whenoutput  
PGND  
7
PGND  
8
LGND  
9
SRCK  
DRAIN4  
SER OUT  
DRAIN7  
10  
11  
DRAIN5 12  
13 DRAIN6  
enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held  
low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for  
cascading of the data from the shift register to additional devices.  
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink  
currentcapability. Whendataintheoutputbuffersislow, theDMOS-transistoroutputsareoff. Whendataishigh,  
the DMOS-transistor outputs have sink current capability.  
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system  
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected  
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND  
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.  
The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount  
(DW) package. The TPIC6A595 is characterized for operation over the operating case temperature range of  
–40°C to 125°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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TPIC6A595NE 替代型号

型号 品牌 替代类型 描述 数据表
TPIC6B596N TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A596NE TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6C595N TI

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 POWER LOGIC 8-BIT SHIFT REGISTER

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