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TPIC6A596DWRG4

更新时间： 2024-12-02 11:08:07
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德州仪器 - TI 移位寄存器
页数 文件大小 规格书
13页 200K
描述
用于增强级联、具有使能/关断功能的 8 位移位寄存器 | DW | 24 | -40 to 125

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TPIC6A596DWRG4 数据手册

 浏览型号TPIC6A596DWRG4的Datasheet PDF文件第2页浏览型号TPIC6A596DWRG4的Datasheet PDF文件第3页浏览型号TPIC6A596DWRG4的Datasheet PDF文件第4页浏览型号TPIC6A596DWRG4的Datasheet PDF文件第5页浏览型号TPIC6A596DWRG4的Datasheet PDF文件第6页浏览型号TPIC6A596DWRG4的Datasheet PDF文件第7页 
TPIC6A596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS094 – MARCH 2000  
NE PACKAGE  
(TOP VIEW)  
Low r  
. . . 1 Ω Typ  
DS(on)  
Output Short-Circuit Protection  
Avalanche Energy . . . 75 mJ  
DRAIN2  
DRAIN3  
SRCLR  
G
DRAIN1  
DRAN0  
SER IN  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
Eight 350-mA DMOS Outputs  
50-V Switching Capability  
V
CC  
Enhanced Cascading for Multiple Stages  
All Registers Cleared With Single Input  
Low Power Consumption  
PGND  
PGND  
RCK  
PGND  
15 PGND  
14  
13  
12  
11  
LGND  
SRCK  
DRAIN4  
DRAIN5  
SER OUT  
DRAIN7  
DRAIN6  
description  
The TPIC6A596 is a monolithic, high-voltage,  
high-current power logic 8-bit shift register  
designed for use in systems that require relatively  
high load power. The device contains a built-in  
voltage clamp on the outputs for inductive  
transient protection. Power driver applications  
include relays, solenoids, and other medium-  
current or high-voltage loads. Each open-drain  
DMOS transistor features an independent  
chopping current-limiting circuit to prevent  
damage in the case of a short circuit.  
DW PACKAGE  
(TOP VIEW)  
DRAIN2  
DRAIN3  
SRCLR  
G
DRAIN1  
DRAIN0  
SER IN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
3
V
4
CC  
PGND  
PGND  
PGND  
PGND  
RCK  
PGND  
5
PGND  
6
PGND  
7
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit, D-type storage  
register. Data transfers through both the shift and  
storage registers on the rising edge of the shift-  
register clock (SRCK) and the register clock  
(RCK), respectively. The storage register  
transfers data to the output buffer when shift-  
PGND  
8
LGND  
9
SRCK  
DRAIN4  
SER OUT  
DRAIN7  
10  
11  
DRAIN5 12  
13 DRAIN6  
register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable  
G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data  
from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the  
device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide  
improved performance for applications where clock signals may be skewed, devices are not located near one  
another, or the system must tolerate electromagnetic interference.  
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink  
currentcapability. Whendataintheoutputbuffersislow, theDMOS-transistoroutputsareoff. Whendataishigh,  
the DMOS-transistor outputs have sink current capability.  
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system  
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected  
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND  
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.  
The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount  
(DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of  
–40°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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TPIC6A596DWRG4 替代型号

型号 品牌 替代类型 描述 数据表
TPIC6A596DW TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER

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 		8-bit addressable latch with 150mA/ch 20-SOIC -40 to 125
TPIC6B259DWRG4 TI

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 		150mA/通道 8 位可寻址锁存器 | DW | 20
TPIC6B259N TI

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 		POWER LOGIC 8-BIT ADDRESSABLE LATCH
TPIC6B273 TI

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 		POWER LOGIC OCTAL D-TYPE LATCH
TPIC6B273DW TI

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 		POWER LOGIC OCTAL D-TYPE LATCH
TPIC6B273DWG4 TI

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 		Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current

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