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TPIC6B595DWG4 PDF预览

TPIC6B595DWG4

更新时间： 2024-12-01 12:47:11
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
15页 808K
描述
POWER LOGIC 8-BIT SHIFT REGISTER

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中文翻译

获取价格

TPIC6B595DWG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.56内置保护：TRANSIENT
输入特性：STANDARD接口集成电路类型：SIPO BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm湿度敏感等级：1
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：OPEN-DRAIN输出电流流向：SINK
最大输出电流：0.15 A标称输出峰值电流：0.5 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.65 mm最大压摆率：0.3 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

TPIC6B595DWG4 数据手册

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SLIS032A − JULY 1995 − REVISED MAY 2005  
D
D
D
D
D
D
D
Low r  
. . . 5 Ω Typical  
DW OR N PACKAGE  
(TOP VIEW)  
DS(on)  
Avalanche Energy . . . 30 mJ  
Eight Power DMOS-Transistor Outputs of  
150-mA Continuous Current  
NC  
NC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
V
GND  
CC  
500-mA Typical Current-Limiting Capability  
Output Clamp Voltage . . . 50 V  
Devices Are Cascadable  
SER IN  
SER OUT  
DRAIN7  
DRAIN6  
DRAIN5  
DRAIN4  
DRAIN0  
DRAIN1  
DRAIN2  
DRAIN3  
SRCLR  
G
Low Power Consumption  
13 SRCK  
description  
12  
11  
RCK  
GND  
GND  
The TPIC6B595 is a monolithic, high-voltage,  
NC − No internal connection  
medium-current power 8-bit shift register  
designed for use in systems that require relatively  
high load power. The device contains a built-in  
voltage clamp on the outputs for inductive  
transient protection. Power driver applications  
include relays, solenoids, and other medium-  
current or high-voltage loads.  
†
logic symbol  
9
EN3  
C2  
G
12  
RCK  
SRG8  
8
SRCLR  
13  
R
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit D-type storage  
register. Data transfers through both the shift and  
storage registers on the rising edge of the  
shift-register clock (SRCK) and the register clock  
(RCK), respectively. The storage register  
transfers data to the output buffer when shift-  
register clear (SRCLR) is high. When SRCLR is  
low, the input shift register is cleared. When output  
enable (G) is held high, all data in the output  
buffers is held low and all drain outputs are off.  
When G is held low, data from the storage register  
is transparent to the output buffers. When data in  
the output buffers is low, the DMOS-transistor  
outputs are off. When data is high, the DMOS-  
transistor outputs have sink-current capability.  
The serial output (SER OUT) allows for cascading  
of the data from the shift register to additional  
devices.  
SRCK  
C1  
1D  
4
5
3
DRAIN0  
DRAIN1  
DRAIN2  
DRAIN3  
DRAIN4  
DRAIN5  
DRAIN6  
DRAIN7  
SER OUT  
2
SER IN  
6
7
14  
15  
16  
17  
18  
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-  
current capability. Each output provides a 500-mA typical current limit at T = 25°C. The current limit decreases  
C
as the junction temperature increases for additional device protection.  
The TPIC6B595 is characterized for operation over the operating case temperature range of −40°C to 125°C.  
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Copyright 1995 − 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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TPIC6B595DWG4 替代型号

型号 品牌 替代类型 描述 数据表
TPIC6B595DWRG4 TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6B595DWR TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6B595N TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER

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