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TPIC6C596DG4 PDF预览

TPIC6C596DG4

更新时间： 2024-11-21 05:52:59
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
17页 489K
描述
POWER LOGIC 8-BIT SHIFT REGISTER

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中文翻译

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TPIC6C596DG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：0.72
其他特性：PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT计数方向：RIGHT
系列：6CJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：30 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：10000000 Hz湿度敏感等级：1
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Shift Registers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：10 MHz
Base Number Matches：1

TPIC6C596DG4 数据手册

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SLIS093C − MARCH 2000 − REVISED APRIL 2005  
D, N, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
D
Low r  
. . . 7 Ω Typ  
DS(on)  
Avalanche Energy . . . 30 mJ  
Eight Power DMOS Transistor Outputs of  
100-mA Continuous Current  
V
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
CC  
SER IN  
SRCK  
250-mA Current Limit Capability  
ESD Protection . . . 2500 V  
DRAIN0  
DRAIN1  
DRAIN2  
DRAIN3  
CLR  
DRAIN7  
DRAIN6  
DRAIN5  
Output Clamp Voltage . . . 33 V  
Enhanced Cascading for Multiple Stages  
All Registers Cleared With Single Input  
Low Power Consumption  
11 DRAIN4  
10 RCK  
G
9
SER OUT  
†
logic symbol  
description  
8
EN3  
C2  
The TPIC6C596 is a monolithic, medium-voltage,  
G
10  
low-current power 8-bit shift register designed for  
use in systems that require relatively moderate  
load power such as LEDs. The device contains a  
built-in voltage clamp on the outputs for inductive  
transient protection. Power driver applications  
include relays, solenoids, and other low-current or  
medium-voltage loads.  
RCK  
SRG8  
7
CLR  
R
15  
SRCK  
C1  
3
2
DRAIN0  
1D  
2
SER IN  
4
5
DRAIN1  
DRAIN2  
DRAIN3  
DRAIN4  
DRAIN5  
DRAIN6  
DRAIN7  
SER OUT  
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit D-type storage  
register. Data transfers through both the shift and  
storage registers on the rising edge of the shift  
register clock (SRCK) and the register clock  
(RCK), respectively. The storage register trans-  
fers data to the output buffer when shift register  
clear (CLR) is high. When CLR is low, all registers  
in the device are cleared. When output enable (G)  
is held high, all data in the output buffers is held  
low and all drain outputs are off. When G is held  
6
11  
12  
13  
14  
9
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,  
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current  
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide  
additional hold time for cascaded applications. This will provide improved performance for applications where  
clock signals may be skewed, devices are not located near one another, or the system must tolerate  
electromagnetic interference.  
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These  
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,  
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated  
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device  
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,  
preferably either V  
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for  
CC  
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2000–2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

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TPIC6C596DG4 替代型号

型号 品牌 替代类型 描述 数据表
TPIC6C595DRG4 TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6C595DR TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6C596DRG4 TI

完全替代

 POWER LOGIC 8-BIT SHIFT REGISTER

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