TPIC6A259DW

更新时间： 2024-11-29 22:28:15

品牌	Logo	应用领域
德州仪器 - TI		锁存器双倍数据速率
页数	文件大小	规格书
11页	182K
描述
POWER LOGIC 8-BIT ADDRESSABLE LATCH

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

TPIC6A259DW 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	0.94	Samacsys Description：	Texas Instruments TPIC6A259DW, 8 Bit Latch, Addressable D Type, Open Drain, 4.5 → 5.5 V, 24-Pin SOIC
系列：	6A	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4	长度：	15.4 mm
逻辑集成电路类型：	LOGIC CIRCUIT	湿度敏感等级：	1
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出特性：	OPEN-DRAIN	输出极性：	INVERTED
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
包装方法：	TUBE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm

TPIC6A259DW 数据手册

TPIC6A259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995

• Low r

. . . 1 Ω Typ

NE PACKAGE

(TOP VIEW)

DS(on)

• Output Short-Circuit Protection

• Avalanche Energy . . . 75 mJ

• Eight 350-mA DMOS Outputs

• 50-V Switching Capability

• Four Distinct Function Modes

• Low Power Consumption

DRAIN2

DRAIN3

DRAIN1

DRAIN0

LGND

PGND

15 PGND

CLR

description

This power logic 8-bit addressable latch controls

open-drain DMOS-transistor outputs and is

designed for general-purpose storage appli-

cations in digital systems. Specific uses include

working registers, serial-holding registers, and

decoders or demultiplexers. This is a multi-

functional device capable of operating as eight

addressable latches or an 8-line demultiplexer

with active-low DMOS outputs. Each open-drain

DMOS transistor features an independent

chopping current-limiting circuit to prevent

damage in the case of a short circuit.

DRAIN4

DRAIN5

DRAIN7

DRAIN6

DW PACKAGE

(TOP VIEW)

DRAIN2

DRAIN3

DRAIN1

DRAIN0

LGND

PGND

CLR

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

as enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS-transistor output inverts the

data input with all unaddressed DMOS-transistor

outputs remaining in their previous states. In the

memory mode, all DMOS-transistor outputs

remain in their previous states and are unaffected

by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latch,

enable G should be held high (inactive) while the

address lines are changing. In the 8-line

demultiplexing mode, the addressed output is

inverted with respect to the D input and all other

outputs are high. In the clear mode, all outputs are

high and unaffected by the address and data

inputs.

DRAIN4

DRAIN7

13 DRAIN6

DRAIN5 12

FUNCTION TABLE

EACH

OTHER

DRAIN

OUTPUT OF

ADDRESSED

DRAIN

INPUTS

CLR G

FUNCTION

Addressable

Latch

Memory

8-Line

Demultiplexer

Clear

LATCH SELECTION TABLE

SELECT INPUTS

DRAIN

ADDRESSED

S2 S1

Separate power ground (PGND) and logic ground

(LGND) terminals are provided to facilitate

maximum system flexibility. All PGND terminals

are internally connected, and each PGND

terminal must be externally connected to the

power system ground in order to minimize

parasitic impedance. A single-point connection

between LGND and PGND must be made

externally in a manner that reduces crosstalk

between the logic and load circuits.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

下载PDF

TPIC6A259DW 替代型号

型号	品牌	替代类型	描述	数据表
TPIC6A259DWRG4	TI	完全替代	350mA/通道 8 位可寻址锁存器 \| DW \| 24 \| -40 to 125
TPIC6A259DWG4	TI	完全替代	350mA/通道 8 位可寻址锁存器 \| DW \| 24 \| -40 to 125
TPIC6A259DWR	TI	类似代替	SPECIALTY LOGIC CIRCUIT, PDSO24, SOIC-24

与TPIC6A259DW相关器件

型号	品牌	获取价格	描述	数据表
TPIC6A259DWG4	TI	获取价格	350mA/通道 8 位可寻址锁存器 \| DW \| 24 \| -40 to 125
TPIC6A259DWR	TI	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO24, SOIC-24
TPIC6A259DWRG4	TI	获取价格	350mA/通道 8 位可寻址锁存器 \| DW \| 24 \| -40 to 125
TPIC6A259NE	TI	获取价格	POWER LOGIC 8-BIT ADDRESSABLE LATCH
TPIC6A595	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A595DW	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A595DWG4	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A595DWR	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A595DWRG4	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER
TPIC6A595NE	TI	获取价格	POWER LOGIC 8-BIT SHIFT REGISTER

与TPIC6A259DW相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

TPIC6A259DW

TPIC6A259DW 技术参数

TPIC6A259DW 数据手册

TPIC6A259DW 替代型号

与TPIC6A259DW相关器件

与TPIC6A259DW相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

TPIC6A259DW

TPIC6A259DW 技术参数

TPIC6A259DW 数据手册

TPIC6A259DW 替代型号

与TPIC6A259DW相关器件

与TPIC6A259DW相关文章

您还可以找

您在本页遇到什么问题？