Datasheet > TPC5160

TPC5160

更新时间： 2024-04-09 18:59:06

品牌	Logo	应用领域
思瑞浦 - 3PEAK		/
页数	文件大小	规格书
23页	2530K
描述
16bit SAR ADC with full differential input

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TPC5160 数据手册

TPC5160

16bit SAR ADC with full differential input

CNV

SCK

SDI1

ADC1 data

ADC2 data

D15

SDO1 & SDI2

SDO2

Busy

ADC1 data

D15

Busy

tconv

tacq

AQUISITION

ADC State

AQUISITION

CONVERSION

Figure 13. Timing Diagram: Daisy-Chain Mode With a Busy Indicator

The SDO pin is driven low when SDI and CNV are both low.

A CNV rising edge with SDI low selects daisy-chain mode, samples the analog input, and causes the device

to enter a conversion phase.

In this mode, CNV must remain high from the start of the conversion until all data bits are read. When started,

the conversion continues with internal clock, regardless of the state of SCK.

However, SCK must be high at the CNV rising edge so that the device generates a busy indicator at the end

of the conversion.

At the end of conversion, every ADC in the chain forces its SDO pin high, providing a low-to-high transition on

̅̅̅̅̅

the IRQ pin of the digital host. The internal shift register of each ADC latches the data available on its SDI pin

and shifts out the next bit of data on its SDO pin on every subsequent SCK falling edge. Therefore, the digital

host receives the interrupt signal followed by the data of ADC N (MSB first), and then the data of

ADC N–1, and so on. A total of (16 × N) + 1 SCK falling edges are required to capture the outputs of all N

devices in the chain. The busy indicator bits of ADC 1 to ADC N–1 do not propagate to the next device in the

chain.

The data is valid on both SCK edges. The rising edge can be used to capture the data, and SCK falling edge

allows a faster reading rate if there is an acceptable hold time.

Power Supply Sequence

The recommended power supply sequence is listed below:

1. Power-up: VDD → VIO → REF → Analog Input. It should be noticed that REF and analog input must be

applied after VDD. However, the device is insensitive to VDD and VIO sequence, which means VIO could

be applied before VDD. Besides, it’s high-Z status for digital input pins without VDD and VIO applied and

digital signal on these pins even would not cause issue even if VDD and VIO are gone;

2. Power-down: Analog Input → REF → VIO → VDD.

www.3peak.com

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