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TP5322 PDF预览

TP5322

更新时间: 2024-11-12 14:53:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
12页 332K
描述
TP5322 is a low threshold enhancement-mode (normally-off) transistor utilizing an advanced vertica

TP5322 数据手册

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TP5322  
P-Channel Enhancement-Mode Vertical DMOS FET  
Features  
General Description  
• –2.4V Maximum Low Threshold  
• High Input Impedance  
The TP5322 low-threshold Enhancement-mode  
(normally-off) transistor uses a vertical DMOS structure  
and a well-proven silicon-gate manufacturing process.  
This combination produces a device with the power  
handling capabilities of bipolar transistors and the high  
input impedance and positive temperature coefficient  
inherent in MOS devices. Characteristic of all MOS  
structures, this device is free from thermal runaway and  
thermally induced secondary breakdown.  
• 110 pF Maximum Low Input Capacitance  
• Fast Switching Speeds  
• Low On-Resistance  
• Free from Secondary Breakdown  
• Low Input and Output Leakage  
Applications  
Microchip’s vertical DMOS FETs are ideally suited for a  
wide range of switching and amplifying applications  
where very low threshold voltage, high breakdown  
voltage, high input impedance, low input capacitance,  
and fast switching speeds are desired.  
• Logic-Level Interfaces (Ideal for TTL and CMOS)  
• Battery-Operated Systems  
• Photovoltaic Drives  
• Analog Switches  
• General Purpose Line Drivers  
Telecommunication Switches  
Package Types  
3-lead SOT-23  
3-lead SOT-89  
(Top view)  
(Top view)  
DRAIN  
DRAIN  
SOURCE  
GATE  
SOURCE  
DRAIN  
GATE  
See Table 2-1 and Table 2-2 for pin information.  
2020 Microchip Technology Inc.  
DS20005973A-page 1  

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