TN1504/TN1506/TN1510
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Features
General Description
These low threshold enhancement-mode (normally-off)
transistors utilize a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This combi-
nationproducesdeviceswiththepowerhandlingcapabilities
of bipolar transistors, and with the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally-induced secondary
breakdown.
► Low threshold - 2.0V max.
► High input impedance
► Low input capacitance - 50pF typical
► Fast switching speeds
► Low on resistance
► Free from secondary breakdown
► Low input and output leakage
► Complementary N- and P-channel devices
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
lowthresholdvoltage,highbreakdownvoltage,highinputim-
pedance, low input capacitance, and fast switching speeds
are desired.
Applications
► Logic level interfaces – ideal for TTL and CMOS
► Solid state relays
► Battery operated systems
► Photo voltaic drives
► Analog switches
► General purpose line drivers
► Telecom switches
Absolute Maximum Ratings
Parameter
Value
BVDSS
BVDGS
20V
Drain-to-source voltage
Drain-to-source voltage
Drain-to-source voltage
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Ordering Information
Order Number
RDS(ON)
(max)
VGS(th)
(max)
ID(ON)
(min)
Device
BVDSS/ BVDGS
Die*
TN1504
TN1506
TN1504NW
TN1506NW
TN1510NW
40V
60V
3.0Ω
3.0Ω
3.0Ω
2.0V
2.0V
2.0V
2.0A
2.0A
2.0A
TN1510
100V
* Die in wafer form.
1