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TN0104N3-GP005 PDF预览

TN0104N3-GP005

更新时间: 2024-10-28 15:54:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP 开关晶体管
页数 文件大小 规格书
7页 730K
描述
SMALL SIGNAL, FET

TN0104N3-GP005 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:CYLINDRICAL, O-PBCY-T3Reach Compliance Code:compliant
风险等级:5.63配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:40 V最大漏极电流 (ID):0.45 A
最大漏源导通电阻:1.8 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):15 pFJEDEC-95代码:TO-92
JESD-30 代码:O-PBCY-T3元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:ROUND
封装形式:CYLINDRICAL极性/信道类型:N-CHANNEL
表面贴装:NO端子形式:THROUGH-HOLE
端子位置:BOTTOM晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

TN0104N3-GP005 数据手册

 浏览型号TN0104N3-GP005的Datasheet PDF文件第2页浏览型号TN0104N3-GP005的Datasheet PDF文件第3页浏览型号TN0104N3-GP005的Datasheet PDF文件第4页浏览型号TN0104N3-GP005的Datasheet PDF文件第5页浏览型号TN0104N3-GP005的Datasheet PDF文件第6页浏览型号TN0104N3-GP005的Datasheet PDF文件第7页 
TN0104  
Supertex inc.  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Low threshold (1.6V max.)  
This low threshold, enhancement-mode (normally-off) transistor  
utilizes a vertical DMOS structure and Supertex’s well-proven,  
silicon-gate manufacturing process. This combination produces  
a device with the power handling capabilities of bipolar  
transistors and with the high input impedance and positive  
temperature coefficient inherent in MOS devices. Characteristic  
of all MOS structures, this device is free from thermal runaway  
and thermally-induced secondary breakdown.  
High input impedance  
Low input capacitance  
Fast switching speeds  
Low on-resistance  
Free from secondary breakdown  
Low input and output leakage  
Applications  
Logic level interfaces – ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Ordering Information  
Product Summary  
RDS(ON)  
(max)  
IDSS  
(min)  
Part Number  
Package Option  
Packing  
BVDSX/BVDGX  
TN0104N3-G  
TO-92  
1000/Bag  
40V  
1.8Ω  
2.0A  
TN0104N3-G P002  
TN0104N3-G P003  
TN0104N3-G P005  
TN0104N3-G P013  
TN0104N3-G P014  
TN0104N8-G  
Pin Configuration  
TO-92  
2000/Reel  
2000/Reel  
DRAIN  
TO-243AA (SOT-89)  
DRAIN  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
SOURCE  
SOURCE  
DRAIN  
GATE  
Absolute Maximum Ratings  
Parameter  
GATE  
Value  
TO-92  
TO-243AA (SOT-89)  
Drain-to-source voltage  
Drain-to-gate voltage  
BVDSS  
BVDGS  
±20V  
Product Marking  
Gate-to-source voltage  
SiTN  
0 1 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Operating and storage temperature  
-55OC to +150OC  
Absolute Maximum Ratings are those values beyond which damage to the device may  
occur. Functional operation under these conditions is not implied. Continuous operation  
of the device at the absolute rating level may affect device reliability. All voltages are  
referenced to device ground.  
Package may or may not include the following marks: Si or  
TO-92  
Typical Thermal Resistance  
W = Code for Week Sealed  
TN1LW  
Package  
θja  
= “Green” Packaging  
Package may or may not include the following marks: Si or  
TO-243AA (SOT-89)  
TO-92  
132OC/W  
133OC/W  
TO-243AA (SOT-89)  
Doc.# DSFP-TN0104  
C080813  
Supertex inc.  
www.supertex.com  

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