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TMS44409-60DGA PDF预览

TMS44409-60DGA

更新时间: 2024-11-11 14:36:23
品牌 Logo 应用领域
德州仪器 - TI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
26页 413K
描述
1MX4 EDO DRAM, 60ns, PDSO20, PLASTIC, SOP-26/20

TMS44409-60DGA 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOP-26/20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92Is Samacsys:N
访问模式:FAST PAGE WITH EDO最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-G20长度:17.14 mm
内存密度:4194304 bit内存集成电路类型:EDO DRAM
内存宽度:4功能数量:1
端口数量:1端子数量:20
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSSOP20/26,.36
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified刷新周期:1024
座面最大高度:1.2 mm自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.105 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:MOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

TMS44409-60DGA 数据手册

 浏览型号TMS44409-60DGA的Datasheet PDF文件第2页浏览型号TMS44409-60DGA的Datasheet PDF文件第3页浏览型号TMS44409-60DGA的Datasheet PDF文件第4页浏览型号TMS44409-60DGA的Datasheet PDF文件第5页浏览型号TMS44409-60DGA的Datasheet PDF文件第6页浏览型号TMS44409-60DGA的Datasheet PDF文件第7页 
TMS44409, TMS44409P  
1048576-WORD BY 4-BIT  
DYNAMIC RANDOM-ACCESS MEMORY  
SMHS563 – JULY1995  
DJ PACKAGE  
(TOP VIEW)  
DGA PACKAGE  
(TOP VIEW)  
Organization . . . 1048576 × 4  
Single 5-V Power Supply (±10% Tolerance)  
Performance Ranges:  
DQ1  
DQ2  
W
RAS  
A9  
1
2
3
4
5
26  
25  
24  
23  
22  
V
DQ1  
DQ2  
W
RAS  
A9  
1
2
3
4
5
26  
25  
24  
23  
22  
V
SS  
SS  
ACCESS ACCESS ACCESS  
TIME TIME TIME  
(t (t (t  
EDO  
CYCLE  
DQ4  
DQ3  
CAS  
OE  
DQ4  
DQ3  
CAS  
OE  
)
)
)
(t  
HPC)  
RAC CAC AA  
(MAX)  
’44409/P-60 60 ns  
’44409/P-70 70 ns  
’44409/P-80 80 ns  
(MAX)  
15 ns  
18 ns  
20 ns  
(MAX)  
30 ns  
35 ns  
40 ns  
(MIN)  
25 ns  
30 ns  
35 ns  
Extended Data Out (EDO) Operation  
CAS-Before-RAS (CBR) Refresh  
3-State Unlatched Output  
A0  
A1  
A2  
A3  
9
18  
17  
16  
15  
14  
A8  
A7  
A6  
A5  
A4  
A0  
A1  
A2  
A3  
9
18  
17  
16  
15  
14  
A8  
A7  
A6  
A5  
A4  
10  
11  
12  
13  
10  
11  
12  
13  
Low Power Dissipation  
All Inputs/Outputs and Clocks are  
TTL-Compatible  
V
V
CC  
CC  
Long Refresh Period  
– 1 024 Cycle Refresh in 16 ns (max)  
– 128 ms on Low Power, Self-Refresh  
Version (TMS44409P Only)  
PIN NOMENCLATURE  
A0A9  
Address Inputs  
Operating Free-Air Temperature Range  
CAS  
Column-Address Strobe  
0°C to 70°C  
DQ1 – DQ4  
OE  
Data In/Data Out  
Output Enable  
Row-Address Strobe  
5-V Supply  
description  
RAS  
V
V
CC  
The TMS44409 is a high-speed 4194304-bit  
dynamic random-access memory (DRAM) orga-  
nized as 1048576 words of four bits each. This  
device features maximum RAS access times of  
60 ns, 70 ns and 80 ns. Maximum power  
consumption is as low as 385 mW operating and  
6 mW standby. All inputs and outputs, including  
Ground  
SS  
W
Write Enable  
clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system  
design. Data out is unlatched to allow greater system flexibility.  
The TMS44409P is a high-speed, low-power, self-refresh version of the TMS44409 DRAM.  
All versions of the TMS44409/P are offered in a 300-mil 20/26 J-lead plastic surface-mount SOJ package (DJ  
suffix) and a 20/26-lead plastic small outline package (DGA suffix). These devices are characterized for  
operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
ADVANCE INFORMATION concerns new products in the sampling or  
preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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1MX4 EDO DRAM, 60ns, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20
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TMS44460-70DJ TI

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1MX4 FAST PAGE DRAM, 70ns, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24