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TMS320LC549GGU-50 PDF预览

TMS320LC549GGU-50

更新时间： 2024-10-28 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
63页 813K
描述
16-BIT, 100MHz, OTHER DSP, PBGA144, PLASTIC, BGA-144

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中文翻译

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TMS320LC549GGU-50 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA144,13X13,32
针数：144Reach Compliance Code：not_compliant
ECCN代码：3A001.A.3HTS代码：8542.31.00.01
风险等级：5.88地址总线宽度：23
桶式移位器：YES位大小：16
边界扫描：YES最大时钟频率：100 MHz
外部数据总线宽度：16格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B144
长度：12 mm低功率模式：YES
端子数量：144封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA144,13X13,32
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not QualifiedRAM（字数）：32768
座面最大高度：1.4 mm子类别：Digital Signal Processors
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320LC549GGU-50 数据手册

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SPRS077B − SEPTEMBER 1998 − REVISED FEBRUARY 2000  
D
D
D
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
D
D
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
Arithmetic Instructions With Parallel Store  
and Parallel Load  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
Conditional Store Instructions  
Fast Return From Interrupt  
On-Chip Peripherals  
− Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
− On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
− Time-Division Multiplexed (TDM) Serial  
Port  
− Buffered Serial Port (BSP)  
− 8-Bit Parallel Host-Port Interface (HPI)  
− One 16-Bit Timer  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
D
D
Data Bus With a Bus Holder Feature  
− External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
Address Bus With a Bus Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
D
D
D
192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
Logic  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM  
D
D
15-ns Single-Cycle Fixed-Point Instruction  
Execution Time (66 MIPS) for 3.3-V Power  
Supply  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply  
D
Block-Memory-Move Instructions for Better  
Program and Data Management  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
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Copyright 2000, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...63

中文翻译

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