Datasheet > TMS320LC549PGE

TMS320LC549PGE

更新时间： 2024-10-25 22:15:39

品牌	Logo	应用领域
德州仪器 - TI		数字信号处理器
页数	文件大小	规格书
61页	789K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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TMS320LC549PGE 数据手册

TMS320LC549

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

Instructions With a 32-Bit Long Word

Operand

Instructions With Two- or Three-Operand

Reads

40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

Arithmetic Instructions With Parallel Store

and Parallel Load

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

– Time-Division Multiplexed (TDM) Serial

Port

– Buffered Serial Port (BSP)

– 8-Bit Parallel Host-Port Interface (HPI)

– One 16-Bit Timer

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Data Bus With a Bus Holder Feature

– External-Input/Output (XIO) Off Control

to Disable the External Data Bus,

Address Bus and Control Signals

Address Bus With a Bus Holder Feature

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

192K × 16-Bit Maximum Addressable

Memory Space (64K Words Program,

64K Words Data, and 64K Words I/O)

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

On-Chip ROM with Some Configurable to

Program/Data Memory

†

IEEE Std 1149.1 (JTAG) Boundary Scan

Logic

Dual-Access On-Chip RAM

Single-Access On-Chip RAM

15-ns Single-Cycle Fixed-Point Instruction

Execution Time (66 MIPS) for 3.3-V Power

Supply

Single-Instruction Repeat and

Block-Repeat Operations for Program Code

12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS) for

3.3-V Power Supply

Block-Memory-Move Instructions for Better

Program and Data Management

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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与TMS320LC549PGE相关器件

型号	品牌	获取价格	描述	数据表
TMS320LC549PGE-40	TI	获取价格	16-BIT, 100MHz, OTHER DSP, PQFP144, PLASTIC, QFP-144
TMS320LC549PGE-50	TI	获取价格	16-BIT, 100MHz, OTHER DSP, PQFP144, PLASTIC, QFP-144
TMS320LC549PGE-66	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320LC549PGE-80	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320LC54X	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC56	TI	获取价格	DIGITAL SIGNAL PROCESSORS
TMS320LC56PZ	TI	获取价格	IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZ50	TI	获取价格	IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZ80	TI	获取价格	IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZA	TI	获取价格	16-BIT, OTHER DSP, PQFP100

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