5秒后页面跳转
捷配首页

Datasheet > TMS320LC549PGE-40
TMS320LC549PGE-40 PDF预览

TMS320LC549PGE-40

更新时间： 2024-10-26 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
63页 813K
描述
16-BIT, 100MHz, OTHER DSP, PQFP144, PLASTIC, QFP-144

阅读下载

中文翻译

获取价格

TMS320LC549PGE-40 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：144
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.82
地址总线宽度：23桶式移位器：YES
边界扫描：YES最大时钟频率：100 MHz
外部数据总线宽度：16格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PQFP-G144
长度：20 mm低功率模式：YES
端子数量：144封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320LC549PGE-40 数据手册

 浏览型号TMS320LC549PGE-40的Datasheet PDF文件第2页浏览型号TMS320LC549PGE-40的Datasheet PDF文件第3页浏览型号TMS320LC549PGE-40的Datasheet PDF文件第4页浏览型号TMS320LC549PGE-40的Datasheet PDF文件第5页浏览型号TMS320LC549PGE-40的Datasheet PDF文件第6页浏览型号TMS320LC549PGE-40的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉꢊ  
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢆ ꢂꢌ ꢔ ꢓꢕꢆ ꢑꢖ ꢒ ꢇꢎ ꢂ ꢂꢒ ꢖ  
SPRS077B − SEPTEMBER 1998 − REVISED FEBRUARY 2000  
D
D
D
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
D
D
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
Arithmetic Instructions With Parallel Store  
and Parallel Load  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
Conditional Store Instructions  
Fast Return From Interrupt  
On-Chip Peripherals  
− Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
− On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
− Time-Division Multiplexed (TDM) Serial  
Port  
− Buffered Serial Port (BSP)  
− 8-Bit Parallel Host-Port Interface (HPI)  
− One 16-Bit Timer  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
D
D
Data Bus With a Bus Holder Feature  
− External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
Address Bus With a Bus Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
D
D
D
192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
Logic  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM  
D
D
15-ns Single-Cycle Fixed-Point Instruction  
Execution Time (66 MIPS) for 3.3-V Power  
Supply  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply  
D
Block-Memory-Move Instructions for Better  
Program and Data Management  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
ꢑ
ꢑ
ꢖ
ꢒ
ꢧ
ꢏ
ꢢ
ꢗ
ꢇ
ꢠ
ꢀ
ꢡ
ꢌ
ꢛ
ꢒ
ꢙ
ꢓ
ꢚ
ꢏ
ꢕ
ꢀ
ꢕ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢀꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2000, Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢪ
ꢞ
ꢌ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢫ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢑ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...63

中文翻译

下载PDF

与TMS320LC549PGE-40相关器件

型号 品牌 获取价格 描述 数据表
TMS320LC549PGE-50 TI

获取价格

 		16-BIT, 100MHz, OTHER DSP, PQFP144, PLASTIC, QFP-144
TMS320LC549PGE-66 TI

获取价格

 		FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320LC549PGE-80 TI

获取价格

 		FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320LC54X TI

获取价格

 		FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC56 TI

获取价格

 		DIGITAL SIGNAL PROCESSORS
TMS320LC56PZ TI

获取价格

 		IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZ50 TI

获取价格

 		IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZ80 TI

获取价格

 		IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
TMS320LC56PZA TI

获取价格

 		16-BIT, OTHER DSP, PQFP100
TMS320LC56PZA50 TI

获取价格

 		16-BIT, 50MHz, OTHER DSP, PQFP100

与TMS320LC549PGE-40相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证