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TMS320C6455DZTZ7

更新时间： 2024-11-23 12:04:47
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德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
256页 1691K
描述
TMS320C6455 Fixed-Point Digital Signal Processor

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TMS320C6455DZTZ7 技术参数

是否无铅： 含铅生命周期：Obsolete
包装说明：FBGA, BGA697,29X29,32Reach Compliance Code：unknown
风险等级：5.63地址总线宽度：
桶式移位器：NO位大小：32
边界扫描：YES外部数据总线宽度：
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B697长度：24 mm
低功率模式：YES端子数量：697
最高工作温度：90 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装等效代码：BGA697,29X29,32封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH电源：1.25 V
认证状态：Not QualifiedRAM（字数）：8192
座面最大高度：3.242 mm子类别：Digital Signal Processors
最大供电电压：1.236 V最小供电电压：1.164 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM宽度：24 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320C6455DZTZ7 数据手册

 浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第2页浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第3页浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第4页浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第5页浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第6页浏览型号TMS320C6455DZTZ7的Datasheet PDF文件第7页 
TMS320C6455  
www.ti.com  
SPRS276M –MAY 2005–REVISED MARCH 2012  
TMS320C6455 Fixed-Point Digital Signal Processor  
Check for Samples: TMS320C6455  
1 Features  
12  
– 1.25-, 2.5-, 3.125-Gbps Link Rates  
• High-Performance Fixed-Point DSP (C6455)  
– Message Passing, DirectIO Support, Error  
Mgmt Extensions, Congestion Control  
– 1.39-, 1.17-, 1-, 0.83-ns Instruction Cycle  
Time  
– IEEE 1149.6 Compliant I/Os  
• DDR2 Memory Controller  
– 720-MHz, 850-MHz, 1-GHz, 1.2-GHz Clock  
Rate  
– Eight 32-Bit Instructions/Cycle  
– 9600 MIPS/MMACS (16-Bits)  
– Commercial Temperature [0°C to 90°C]  
– Extended Temperature [-40°C to 105°C]  
• TMS320C64x+™ DSP Core  
– Interfaces to DDR2-533 SDRAM  
– 32-Bit/16-Bit, 533-MHz (data rate) Bus  
– 512M-Byte Total Addressable External  
Memory Space  
• EDMA3 Controller (64 Independent Channels)  
• 32-/16-Bit Host-Port Interface (HPI)  
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
– Dedicated SPLOOP Instruction  
– Compact Instructions (16-Bit)  
– Instruction Set Enhancements  
– Exception Handling  
Conforms to PCI Local Bus Specification (v2.3)  
• One Inter-Integrated Circuit (I2C) Bus  
• Two McBSPs  
• TMS320C64x+ Megamodule L1/L2 Memory  
Architecture:  
• 10/100/1000 Mb/s Ethernet MAC (EMAC)  
– IEEE 802.3 Compliant  
– 256K-Bit (32K-Byte) L1P Program Cache  
[Direct Mapped]  
– Supports Multiple Media Independent  
Interfaces (MII, GMII, RMII, and RGMII)  
– 256K-Bit (32K-Byte) L1D Data Cache  
[2-Way Set-Associative]  
– 8 Independent Transmit (TX) and  
8 Independent Receive (RX) Channels  
– 16M-Bit (2048K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
• Two 64-Bit General-Purpose Timers,  
Configurable as Four 32-Bit Timers  
• UTOPIA  
– 256K-Bit (32K-Byte) L2 ROM  
– Time Stamp Counter  
• Enhanced Viterbi Decoder Coprocessor (VCP2)  
– Supports Over 694 7.95-Kbps AMR  
– Programmable Code Parameters  
• Enhanced Turbo Decoder Coprocessor (TCP2)  
– UTOPIA Level 2 Slave ATM Controller  
– 8-Bit Transmit and Receive Operations up to  
50 MHz per Direction  
– User-Defined Cell Format up to 64 Bytes  
• 16 General-Purpose I/O (GPIO) Pins  
• System PLL and PLL Controller  
• Secondary PLL and PLL Controller, Dedicated  
to EMAC and DDR2 Memory Controller  
• Advanced Event Triggering (AET) Compatible  
• Trace-Enabled Device  
• IEEE-1149.1 (JTAG™) Boundary-Scan-  
Compatible  
– Supports up to Eight 2-Mbps 3GPP  
(6 Iterations)  
– Programmable Turbo Code and Decoding  
Parameters  
• Endianess: Little Endian, Big Endian  
• 64-Bit External Memory Interface (EMIFA)  
– Glueless Interface to Asynchronous  
Memories (SRAM, Flash, and EEPROM) and  
Synchronous Memories (SBSRAM, ZBT  
SRAM)  
– Supports Interface to Standard Sync Devices  
and Custom Logic  
• 697-Pin Ball Grid Array (BGA) Package  
(CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch  
• 0.09-μm/7-Level Cu Metal Process (CMOS)  
(FPGA, CPLD, ASICs, etc.)  
– 32M-Byte Total Addressable External  
Memory Space  
• 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os,  
1.25-/1.2-V Internal  
• Four 1x Serial RapidIO® Links (or One 4x),  
v1.2 Compliant  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2005–2012, Texas Instruments Incorporated  
 
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