TMS320C6455
Fixed-Point Digital Signal Processor
SPRS276H–MAY 2005–REVISED OCTOBER 2007
1 Features
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High-Performance Fixed-Point DSP (C6455)
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Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
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1.39-, 1.17, 1-, and 0.83-ns Instruction Cycle
Time
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1.25-, 2.5-, 3.125-Gbps Link Rates
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720-MHz, 850-MHz, 1-GHz, and 1.2-GHz
Clock Rate
Message Passing, DirectIO Support, Error
Management Extensions, and Congestion
Control
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Eight 32-Bit Instructions/Cycle
9600 MIPS/MMACS (16-Bits)
Commercial Temperature [0°C to 90°C]
Extended Temperature [-40°C to 105°C]
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IEEE 1149.6 Compliant I/Os
DDR2 Memory Controller
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Interfaces to DDR2-533 SDRAM
32-Bit/16-Bit, 533-MHz (data rate) Bus
512M-Byte Total Addressable External
Memory Space
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TMS320C64x+™ DSP Core
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Dedicated SPLOOP Instruction
Compact Instructions (16-Bit)
Instruction Set Enhancements
Exception Handling
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EDMA3 Controller (64 Independent Channels)
32-/16-Bit Host-Port Interface (HPI)
32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Local Bus Specification
(version 2.3)
TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
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256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
16M-Bit (2096K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
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One Inter-Integrated Circuit (I2C) Bus
Two McBSPs
10/100/1000 Mb/s Ethernet MAC (EMAC)
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IEEE 802.3 Compliant
Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
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256K-Bit (32K-Byte) L2 ROM
Time Stamp Counter
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Enhanced VCP2
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8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
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Supports Over 694 7.95-Kbps AMR
Programmable Code Parameters
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Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
Enhanced Turbo Decoder Coprocessor (TCP2)
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Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
UTOPIA
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UTOPIA Level 2 Slave ATM Controller
8-Bit Transmit and Receive Operations up
to 50 MHz per Direction
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Programmable Turbo Code and Decoding
Parameters
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Endianess: Little Endian, Big Endian
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User-Defined Cell Format up to 64 Bytes
64-Bit External Memory Interface (EMIFA)
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16 General-Purpose I/O (GPIO) Pins
System PLL and PLL Controller
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Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
SRAM)
Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
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Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)
32M-Byte Total Addressable External
Memory Space
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Advanced Event Triggering (AET) Compatible
Trace-Enabled Device
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
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697-Pin Ball Grid Array (BGA) Package
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch
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0.09-μm/7-Level Cu Metal Process (CMOS)
3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V
Internal
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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