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TMS320C6455ZTZ PDF预览

TMS320C6455ZTZ

更新时间： 2024-11-26 05:24:27
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
250页 1976K
描述
Fixed-Point Digital Signal Processor

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TMS320C6455ZTZ 技术参数

生命周期：Obsolete包装说明：FBGA, BGA697,29X29,32
Reach Compliance Code：unknown风险等级：5.84
位大小：32格式：FIXED POINT
JESD-30 代码：S-PBGA-B697端子数量：697
最高工作温度：90 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装等效代码：BGA697,29X29,32封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH电源：1.2 V
认证状态：Not QualifiedRAM（字数）：32768
子类别：Digital Signal Processors标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
Base Number Matches：1

TMS320C6455ZTZ 数据手册

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TMS320C6455  
Fixed-Point Digital Signal Processor  
SPRS276H–MAY 2005–REVISED OCTOBER 2007  
1 Features  
•
High-Performance Fixed-Point DSP (C6455)  
•
•
Four 1x Serial RapidIO® Links (or One 4x),  
v1.2 Compliant  
–
1.39-, 1.17, 1-, and 0.83-ns Instruction Cycle  
Time  
–
–
1.25-, 2.5-, 3.125-Gbps Link Rates  
–
720-MHz, 850-MHz, 1-GHz, and 1.2-GHz  
Clock Rate  
Message Passing, DirectIO Support, Error  
Management Extensions, and Congestion  
Control  
–
–
–
–
Eight 32-Bit Instructions/Cycle  
9600 MIPS/MMACS (16-Bits)  
Commercial Temperature [0°C to 90°C]  
Extended Temperature [-40°C to 105°C]  
–
IEEE 1149.6 Compliant I/Os  
DDR2 Memory Controller  
–
–
–
Interfaces to DDR2-533 SDRAM  
32-Bit/16-Bit, 533-MHz (data rate) Bus  
512M-Byte Total Addressable External  
Memory Space  
•
•
TMS320C64x+™ DSP Core  
–
–
–
–
Dedicated SPLOOP Instruction  
Compact Instructions (16-Bit)  
Instruction Set Enhancements  
Exception Handling  
•
•
•
EDMA3 Controller (64 Independent Channels)  
32-/16-Bit Host-Port Interface (HPI)  
32-Bit 33-/66-MHz, 3.3-V Peripheral Component  
Interconnect (PCI) Master/Slave Interface  
Conforms to PCI Local Bus Specification  
(version 2.3)  
TMS320C64x+ Megamodule L1/L2 Memory  
Architecture:  
–
–
–
256K-Bit (32K-Byte) L1P Program Cache  
[Direct Mapped]  
256K-Bit (32K-Byte) L1D Data Cache  
[2-Way Set-Associative]  
16M-Bit (2096K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
•
•
•
One Inter-Integrated Circuit (I2C) Bus  
Two McBSPs  
10/100/1000 Mb/s Ethernet MAC (EMAC)  
–
–
IEEE 802.3 Compliant  
Supports Multiple Media Independent  
Interfaces (MII, GMII, RMII, and RGMII)  
–
–
256K-Bit (32K-Byte) L2 ROM  
Time Stamp Counter  
•
•
Enhanced VCP2  
–
8 Independent Transmit (TX) and  
8 Independent Receive (RX) Channels  
–
–
Supports Over 694 7.95-Kbps AMR  
Programmable Code Parameters  
•
•
Two 64-Bit General-Purpose Timers,  
Configurable as Four 32-Bit Timers  
Enhanced Turbo Decoder Coprocessor (TCP2)  
–
Supports up to Eight 2-Mbps 3GPP  
(6 Iterations)  
UTOPIA  
–
–
UTOPIA Level 2 Slave ATM Controller  
8-Bit Transmit and Receive Operations up  
to 50 MHz per Direction  
–
Programmable Turbo Code and Decoding  
Parameters  
•
•
Endianess: Little Endian, Big Endian  
–
User-Defined Cell Format up to 64 Bytes  
64-Bit External Memory Interface (EMIFA)  
•
•
•
16 General-Purpose I/O (GPIO) Pins  
System PLL and PLL Controller  
–
Glueless Interface to Asynchronous  
Memories (SRAM, Flash, and EEPROM) and  
Synchronous Memories (SBSRAM, ZBT  
SRAM)  
Secondary PLL and PLL Controller, Dedicated  
to EMAC and DDR2 Memory Controller  
–
–
Supports Interface to Standard Sync  
Devices and Custom Logic (FPGA, CPLD,  
ASICs, etc.)  
32M-Byte Total Addressable External  
Memory Space  
•
•
•
Advanced Event Triggering (AET) Compatible  
Trace-Enabled Device  
IEEE-1149.1 (JTAG™)  
Boundary-Scan-Compatible  
•
697-Pin Ball Grid Array (BGA) Package  
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch  
•
•
0.09-μm/7-Level Cu Metal Process (CMOS)  
3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V  
Internal  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2007, Texas Instruments Incorporated  
 
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