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TMS320C6203B PDF预览

TMS320C6203B

更新时间: 2024-10-27 05:29:11
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
106页 1664K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6203B 数据手册

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TMS320C6203B  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS086M JANUARY 1999 REVISED MARCH 2004  
D
D
High-Performance Fixed-Point Digital  
Signal Processor (DSP) TMS320C62x  
4-, 3.33-ns Instruction Cycle Time  
250-, 300-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
2000, 2400 MIPS  
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
D
D
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
32-Bit Expansion Bus (XBus)  
Glueless/Low-Glue Interface to Popular  
PCI Bridge Chips  
Glueless/Low-Glue Interface to Popular  
Synchronous or Asynchronous  
Microprocessor Buses  
Master/Slave Functionality  
Glueless Interface to Synchronous FIFOs  
and Asynchronous Peripherals  
C6203B and C6202 GLS Ball Grid Array  
(BGA) Packages are Pin-Compatible With  
the C6204 GLW BGA Package  
D
D
C6203B and C6202B GNZ and GNY  
Packages are Pin-Compatible  
VelociTIAdvanced Very-Long-Instruction-  
Word (VLIW) C62xDSP Core  
Eight Highly Independent Functional  
Units:  
D
Three Multichannel Buffered Serial Ports  
(McBSPs)  
Six ALUs (32-/40-Bit)  
Two 16-Bit Multipliers (32-Bit Result)  
Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
Direct Interface to T1/E1, MVIP, SCSA  
Framers  
ST-Bus-Switching Compatible  
Up to 256 Channels Each  
AC97-Compatible  
Serial-Peripheral Interface (SPI)  
Compatible (Motorola)  
Two 32-Bit General-Purpose Timers  
D
D
D
Instruction Set Features  
Byte-Addressable (8-, 16-, 32-Bit Data)  
8-Bit Overflow Protection  
Saturation  
Bit-Field Extract, Set, Clear  
Bit-Counting  
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
352-Pin BGA Package (GNZ)  
384-Pin BGA Package (GLS)  
384-Pin BGA Package (GNY)  
D
D
D
D
Normalization  
7M-Bit On-Chip SRAM  
3M-Bit Internal Program/Cache  
(96K 32-Bit Instructions)  
4M-Bit Dual-Access Internal Data  
(512K Bytes)  
0.15-µm/5-Level Metal Process  
CMOS Technology  
D
3.3-V I/Os, 1.5-V Internal  
Organized as Two 256K-Byte Blocks  
for Improved Concurrency  
32-Bit External Memory Interface (EMIF)  
Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
52M-Byte Addressable External Memory  
Space  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
For more details, see the GLS BGA package bottom view.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2004, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443  

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