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TMS320C6203CGNZ250 PDF预览

TMS320C6203CGNZ250

更新时间: 2024-10-26 23:36:27
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其他 - ETC 外围集成电路
页数 文件大小 规格书
90页 1368K
描述
DSP|32-BIT|CMOS|BGA|352PIN|PLASTIC

TMS320C6203CGNZ250 数据手册

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TMS320C6203B, TMS320C6203C  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS086F – JANUARY 1999 – REVISED SEPTEMBER 2001  
D
High-Performance Fixed-Point Digital  
Signal Processor (DSP) – TMS320C62x  
– 4-, 3.33-ns Instruction Cycle Time  
– 250-, 300-MHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– 2000, 2400 MIPS  
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
D
D
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
32-Bit Expansion Bus (XBus)  
– Glueless/Low-Glue Interface to Popular  
PCI Bridge Chips  
– Glueless/Low-Glue Interface to Popular  
Synchronous or Asynchronous  
Microprocessor Buses  
– Master/Slave Functionality  
– Glueless Interface to Synchronous FIFOs  
and Asynchronous Peripherals  
D
D
C6203B and C6202/02B GLS Ball Grid Array  
(BGA) Packages are Pin-Compatible With  
the C6204 GLW BGA Package  
VelociTI Advanced Very-Long-Instruction-  
Word (VLIW) C62x DSP Core  
– Eight Highly Independent Functional  
Units:  
– Six ALUs (32-/40-Bit)  
– Two 16-Bit Multipliers (32-Bit Result)  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
D
Three Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial-Peripheral Interface (SPI)  
Compatible (Motorola )  
D
D
D
Instruction Set Features  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 8-Bit Overflow Protection  
– Saturation  
– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
D
D
D
D
D
Two 32-Bit General-Purpose Timers  
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
7M-Bit On-Chip SRAM  
– 3M-Bit Internal Program/Cache  
(96K 32-Bit Instructions)  
– 4M-Bit Dual-Access Internal Data  
(512K Bytes)  
352-Pin BGA Package (GNZ) (C6203C only)  
384-Pin BGA Package (GLS) (C6203B only)  
384-Pin BGA Package (GNY)  
[C6203B and C6203C]  
– Organized as Two 256K-Byte Blocks  
for Improved Concurrency  
D
0.12-µm/6-Level Metal Process (C6203C)  
D
0.15-µm/5-Level Metal Process (C6203B)  
– CMOS Technology  
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
– 52M-Byte Addressable External Memory  
Space  
D
D
3.3-V I/Os, 1.2-V Internal (C6203C)  
3.3-V I/Os, 1.5-V Internal (C6203B)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
For more details, see the GLS BGA package bottom view.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2001, Texas Instruments Incorporated  
This document contains information on products in more than one phase  
of development. The status of each device is indicated on the page(s)  
specifying its electrical characteristics.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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