TLV320ADC3001
www.ti.com
SLAS548C –OCTOBER 2008–REVISED APRIL 2011
Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
Check for Samples: TLV320ADC3001
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FEATURES
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2,24-mm × 2,16-mm NanoFree™ 16-Ball
16-YZH Wafer Chip Scale Package (WCSP)
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Stereo Audio ADC
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92-dBA Signal-to-Noise Ratio
APPLICATIONS
Supports ADC Sample Rates From 8 kHz to
96 kHz
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Wireless Handsets
Portable Low-Power Audio Systems
Noise Cancellation Systems
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Instruction-Programmable Embedded miniDSP
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Flexible Digital Filtering With RAM
Programmable Coefficient, Instructions, and
Built-In Standard Modes
Front-End Voice or Audio Processor for Digital
Audio
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Low-Latency IIR Filters for Voice
Linear Phase FIR Filters for Audio
DESCRIPTION
The TLV320ADC3001 is a low-power, stereo audio
analog-to-digital converter (ADC) supporting sampling
rates from 8 kHz to 96 kHz with an integrated
programmable-gain amplifier providing up to 40 dB
analog gain or AGC. A programmable miniDSP is
provided for custom audio processing. Front-end
input coarse attenuation of 0 dB, –6 dB, or off, is also
Additional Programmable IIR Filters for EQ,
Noise Cancellation, or Reduction
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Up to 128 Programmable ADC Digital Filter
Coefficients
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Three Audio Inputs With Configurable
Automatic Gain Control (AGC)
provided. The inputs are programmable in
a
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Programmable in Single-Ended or Fully
Differential Configurations
combination of single-ended or fully differential
configurations. Extensive register-based power
control is available via I2C, enabling mono or stereo
recording. Low power consumption makes the
TLV320ADC3001 ideal for battery-powered portable
equipment.
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Can Be Driven Hi-Z for Easy Interoperability
With Other Audio ICs
Low Power Consumption and Extensive
Modular Power Control:
The AGC programs to a wide range of attack
(7 ms–1.4 s) and decay (50 ms–22.4 s) times. A
programmable noise gate function is included to
avoid noise pumping. Low-latency IIR filters optimized
for voice and telephony are available, as well as
linear-phase FIR filters optimized for audio.
Programmable IIR filters are also available and may
be used for sound equalization, or to remove noise
components. The audio serial bus can be
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6-mW Mono Record 8-kHz
11-mW Stereo Record, 8-kHz
10-mW Mono Record, 48-kHz
17-mW Stereo Record, 48-kHz
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Programmable Microphone Bias
Programmable PLL for Clock Generation
I2C™ Control Bus
Audio Serial Data Bus Supports I2S,
Left/Right-Justified, DSP, PCM, and TDM
Modes
programmed
to
support
I2S,
left-justified,
right-justified, DSP, PCM, and TDM modes. The
audio bus may be operated in either master or slave
mode.
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Power Supplies:
A programmable integrated PLL is included for
flexible clock generation and support for all standard
audio rates from a wide range of available MCLKs,
varying from 512 kHz to 50 MHz, including the most
popular cases of 12-MHz, 13-MHz, 16-MHz,
19.2-MHz, and 19.68-MHz system clocks.
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Analog: 2.6 V–3.6 V.
Digital: Core: 1.65 V–1.95 V,
I/O: 1.1 V–3.6 V
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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NanoFree, PurePath Studio are trademarks of Texas Instruments.
I2C is a trademark of NXP B.V.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated