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TLV320AD12APZ PDF预览

TLV320AD12APZ

更新时间: 2024-11-22 22:40:27
品牌 Logo 应用领域
德州仪器 - TI 解码器编解码器电信集成电路
页数 文件大小 规格书
21页 314K
描述
3.3-V INTEGRATED ADSL CODEC

TLV320AD12APZ 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:100Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
滤波器:YESJESD-30 代码:S-PQFP-G100
长度:14 mm功能数量:1
端子数量:100工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ADSL CODEC温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

TLV320AD12APZ 数据手册

 浏览型号TLV320AD12APZ的Datasheet PDF文件第2页浏览型号TLV320AD12APZ的Datasheet PDF文件第3页浏览型号TLV320AD12APZ的Datasheet PDF文件第4页浏览型号TLV320AD12APZ的Datasheet PDF文件第5页浏览型号TLV320AD12APZ的Datasheet PDF文件第6页浏览型号TLV320AD12APZ的Datasheet PDF文件第7页 
TLV320AD12A  
3.3-V INTEGRATED ADSL CODEC  
SLWS088B – JULY 1999 – REVISED MARCH 2000  
Complete Discrete Multitone (DMT)-Based  
Asymmetric Digital Subscriber Line (ADSL)  
Coder/Decoder (Codec) Solution  
2s-Complement Data Format  
Selectable 2.2-MSPS or 4.4-MSPS Parallel  
Data Transfer Rate  
Complies With ANSI T1.413, Issue 2 and  
ITU G.992.1  
Serial Configuration Port  
Eight General-Purpose (GP) Output  
Terminals  
Supports up to 8-Mbit/s Downstream and  
800-kbit/s Upstream Duplex  
Supports Multiple-Channel Configuration  
Single 3.3-V Supply  
Integrated 14-Bit Converter for  
Transmitter/Receiver  
Hardware/Software Power Down  
40°C to 85°C Operation  
Integrated Transmit/Receive (TX/RX)  
Channel Filters  
Packaged in 100-Pin Plastic Quad Flatpack  
Integrated TX/RX Attenuation/Gain  
Integrated Reference  
High-Speed Parallel Interface  
description  
TheTLV320AD12Aisahigh-speedcoder/decoder(codec)forcentraloffice-side(CO)discrete-multitone(DMT)  
asymmetric-digitalsubscriber line (ADSL) access that supports ANSI Std T1.413, Issue 2 and ITU G.992.1. The  
codec is a low-power device comprised of five major functional blocks: transmitter (TX), receiver (RX), clock,  
reference, and host interface.  
Thetransmitchannelconsistsofa25.875-kHzto1.104-MHzdigitalband-passfilter, a14-bit, 8.832-MSPSDAC,  
a 1.104-MHz analog low-pass filter, and a transmit attenuator. The receiver channel consists of a two  
programmable-gain-amplifier stages (PGA), a 138-kHz analog low-pass filter, a 14-bit, 4.416-MSPS ADC, a  
138-kHz digital low-pass filter. An onboard reference circuit generates 1.5-V reference voltage for the  
converters.  
The codec has two interface ports: a parallel port for data transfer, and a serial port for control. The parallel port  
is 16 bits wide, and is reserved for moving data between the codec and a DSP, such as the TMS320C6XX.  
Configuration is done via the serial port. A special interface scheme enables multichannel system design. The  
TLV320AD12A can be powered down via a dedicated terminal or through software control to reduce heat  
dissipation. Additionally, there is a general-purpose (GP) port consisting of eight output terminals for control of  
external circuitry.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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