ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢃꢇ ꢈꢁꢉ ꢊ
ꢄ ꢅꢋꢅ ꢊ ꢌ ꢍ ꢎꢊꢉ ꢏꢐꢑ ꢌꢁ ꢌꢑꢒ ꢎꢅꢓꢐ ꢔꢎ ꢔꢍꢑ ꢐꢏꢅ ꢏꢊꢉ ꢏꢐ ꢀ ꢐꢌꢎꢑ ꢋ ꢊꢀ ꢀꢏ ꢐ
SLLS627− SEPTEMBER 2004
D
Integrated Asynchronous Communications
Element (ACE) Compatible With PCMCIA
PC Card Standard Release 2.01
D
Fully Programmable Serial-Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit Generation
and Detection
D
D
Consists of a Single TL16C550 ACE Plus
PCMCIA Interface Logic
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud-Rate Generation
Provides Common I-Bus/Z-Bus
Microcontroller Inputs for Most Intel and
D
D
D
Fully Prioritized Interrupt System Controls
Modem Control Functions
Zilog Subsystems
D
D
D
D
Fully Programmable 256-Byte Card
Information Structure (CIS) and 8-Byte Card
Configuration Register (CCR)
Provides TL16C450 Mode at Reset Plus
Selectable Normal TL16C550 Operation or
Extended 64-Byte FIFO Mode
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop and
Parity) to or From Serial Data Stream
D
Selectable Auto-RTS Mode Deactivates
RTS at 14 Bytes in 550 Mode and at
56 Bytes in Extended 550 Mode
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D
D
Selectable Auto-CTS Mode Deactivates
Serial Transfers When CTS is Inactive
Subsystem Selectable Serial-Bypass Mode
Provides Subsystem With Direct Parallel
Access to the FIFOs
Available in 100 Pin Thin Quad Flatpack
(PZ) Package
description
The TL16PC564BLVI is designed to provide all the functions necessary for a Personal Computer Memory Card
International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface.
This interface provides a serial-to-parallel conversion for data to and from a modem coder-decoder/digital signal
processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A computer central processing unit
(CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element
(ACE) interface at any point in the operation. Reported status information includes the type of transfer operation
in process, the status of the operation, and any error conditions encountered.
Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration
registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both
the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically
erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute
memory is initialized by the subsystem.
The TL16PC564BLVI uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out
(FIFO) memory and a 64 × 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in
order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART
registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows
the subsystem to read UART status information.
A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial
portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt
operation is not affected in this mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a registered trademark of Intel System, Inc.
Zilog is a registered trademark of Zilog Incorporated
MicroStar BGA is a trademark of Texas Instruments Incorporated.
ꢄ
ꢄ
ꢐ
ꢔ
ꢥ
ꢕ
ꢠ
ꢍ
ꢅ
ꢞ
ꢀ
ꢟ
ꢊ
ꢙ
ꢔ
ꢗ
ꢎ
ꢘ
ꢕ
ꢌ
ꢀ
ꢌ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢀꢡ
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 2004, Texas Instruments Incorporated
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢨ
ꢜ
ꢊ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢩ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢄ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
