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TL16PNP550A_08 PDF预览

TL16PNP550A_08

更新时间: 2024-09-15 02:58:43
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德州仪器 - TI /
页数 文件大小 规格书
40页 546K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

TL16PNP550A_08 数据手册

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TL16PNP550A  
ASYNCHRONOUS COMMUNICATIONS ELEMENT  
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL  
SLLS190B – MARCH 1995 – REVISED MARCH 1996  
PnP Card Autoconfiguration Sequence  
On-Chip I/O Port Address Decoding  
Compliant  
In PnP Bypass Mode, 6 External Terminals  
Configure the I/O Base Address and  
Interrupt Mapping  
External Terminal-to-Bypass PnP  
Autoconfiguration Sequence  
Adds or Deletes Standard Asynchronous  
Communication Bits (Start, Stop, and  
Parity) to or From the Serial Data Stream  
In UART Bypass Mode, the Stand-Alone  
PnP Controller is Configured With One  
Logical Device  
Independent Control of Transmit, Receive,  
Line Status, and Data Set Interrupts on  
Each Channel  
Provides 10-Interrupts IRQ3IRQ7,  
IRQ9IRQ12, IRQ15  
Simple 3-Pin Interface to SGS-Thomson  
EEPROM 2K/4K ST93C56/66  
Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity-Bit Generation  
and Detection  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (DC to 1 Mbit Per  
Second)  
High Output Current Drive. No External  
Buffer Needed for Data and Interrupt  
Signals  
Programmable Auto-RTS and Auto-CTS  
In Auto-CTS Mode, CTS Controls  
Transmitter  
In Auto-RTS Mode, Receiver FIFO Contents  
and Threshold Control RTS  
False Start Bit Detection  
Complete Status Reporting Capabilities  
The Serial and Modem Control Outputs  
Drive a 1-Meter RJ11 Cable Directly if  
Equipment Is on the Same Power Drop  
3-State Outputs Provide TTL Drive for  
Bidirectional Data Bus and Interrupt Lines  
Line Break Generation and Detection  
Capable of Running With All Existing  
TL16C450 Software  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
– Break, Parity, Overrun, and Framing  
Error Simulation  
After Reset, All Registers Are Identical to  
the TL16C450 Register Set  
Clock Prescalar Allows 22-MHz Oscillator  
Clock to be Divided by 12, 6, 3, or 1  
Fully Prioritized Interrupt System Controls  
In the TL16C450 Mode, Hold and Shift  
Registers Eliminate the Need for Precise  
Synchronization Between the CPU and  
Serial Data  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
Transmitter and Receiver Run at the Same  
Speed  
Programmable Baud Rate Generator Allows  
Division of Any Input Reference Clock by 1  
Up to 16-MHz Clock Rate for Up to 1-Mbaud  
Operation for the Internal ACE  
16  
to (2 1) and Generates an Internal 16×  
Available in 68-Pin PLCC  
Clock  
description  
The TL16PNP550A is a functional upgrade of the TL16C550C asynchronous communications element (ACE),  
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up  
(character or TL16C450 mode), the TL16PNP550A, like the TL16C550C, can be placed in an alternate mode  
(FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted  
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SGS-Thomson is a trademark of SGS-Thomson Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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