Datasheet > TL16PC564BLVIPZ

TL16PC564BLVIPZ

更新时间： 2024-11-22 20:05:15

品牌	Logo	应用领域
德州仪器 - TI		通信时钟数据传输 PC 外围集成电路
页数	文件大小	规格书
35页	711K
描述
PCM Universal Async Receiver Transmitter 100-LQFP -40 to 85

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TL16PC564BLVIPZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.82	其他特性：	ALSO OPERATES 3V SUPPLY
地址总线宽度：	10	边界扫描：	NO
总线兼容性：	PCMCIA	最大时钟频率：	60 MHz
通信协议：	ASYNC, BIT	最大数据传输速率：	0.0140380859375 MBps
外部数据总线宽度：	8	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e4	长度：	14 mm
低功率模式：	NO	湿度敏感等级：	3
串行 I/O 数：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3/5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Serial IO/Communication Controllers
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

TL16PC564BLVIPZ 数据手册

Not Recommended For New Designs

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SLLS627− SEPTEMBER 2004

Integrated Asynchronous Communications

Element (ACE) Compatible With PCMCIA

PC Card Standard Release 2.01

Fully Programmable Serial-Interface

Characteristics:

− 5-, 6-, 7-, or 8-Bit Characters

− Even-, Odd-, or No-Parity Bit Generation

and Detection

Consists of a Single TL16C550 ACE Plus

PCMCIA Interface Logic

− 1-, 1 1/2-, or 2-Stop Bit Generation

− Baud-Rate Generation

Provides Common I-Bus/Z-Bus



Microcontroller Inputs for Most Intel and

Fully Prioritized Interrupt System Controls

Modem Control Functions



Zilog Subsystems

Fully Programmable 256-Byte Card

Information Structure (CIS) and 8-Byte Card

Configuration Register (CCR)

Provides TL16C450 Mode at Reset Plus

Selectable Normal TL16C550 Operation or

Extended 64-Byte FIFO Mode

Adds or Deletes Standard Asynchronous

Communication Bits (Start, Stop and

Parity) to or From Serial Data Stream

Selectable Auto-RTS Mode Deactivates

RTS at 14 Bytes in 550 Mode and at

56 Bytes in Extended 550 Mode

Independently Controlled Transmit,

Receive, Line Status, and Data Set

Interrupts

Selectable Auto-CTS Mode Deactivates

Serial Transfers When CTS is Inactive

Subsystem Selectable Serial-Bypass Mode

Provides Subsystem With Direct Parallel

Access to the FIFOs

Available in 100 Pin Thin Quad Flatpack

(PZ) Package

description

The TL16PC564BLVI is designed to provide all the functions necessary for a Personal Computer Memory Card

International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface.

This interface provides a serial-to-parallel conversion for data to and from a modem coder-decoder/digital signal

processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A computer central processing unit

(CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element

(ACE) interface at any point in the operation. Reported status information includes the type of transfer operation

in process, the status of the operation, and any error conditions encountered.

Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration

registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both

the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically

erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute

memory is initialized by the subsystem.

The TL16PC564BLVI uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out

(FIFO) memory and a 64 × 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in

order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART

registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows

the subsystem to read UART status information.

A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial

portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt

operation is not affected in this mode.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a registered trademark of Intel System, Inc.

Zilog is a registered trademark of Zilog Incorporated

MicroStar BGA is a trademark of Texas Instruments Incorporated.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...35

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与TL16PC564BLVIPZ相关器件

型号	品牌	获取价格	描述	数据表
TL16PC564BLVPZ	TI	获取价格	PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
TL16PC564BPZ	TI	获取价格	PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
TL16PIR552	TI	获取价格	DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
TL16PIR552PH	TI	获取价格	DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
TL16PIR552PHL	TI	获取价格	2 CHANNEL(S), 1Mbps, SERIAL COMM CONTROLLER, PQFP80
TL16PNP100A	TI	获取价格	STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
TL16PNP100ACFN	TI	获取价格	ISA BUS CONTROLLER, PQCC44
TL16PNP100ACPT	TI	获取价格	ISA BUS CONTROLLER, PQFP48
TL16PNP100AFN	ROCHESTER	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, PQCC44, PLASTIC, LCC-44
TL16PNP100AFN	TI	获取价格	STANDALONE PLUG-AND-PLAY

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