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TL16C2550

更新时间: 2024-11-17 21:55:23
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德州仪器 - TI 先进先出芯片
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34页 408K
描述
2.5-V to 5-V DUAL UART WITH 16-BYTE FIFOS

TL16C2550 数据手册

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TL16C2550  
www.ti.com  
SLWS161JUNE 2005  
2.5-V to 5-V DUAL UART WITH 16-BYTE FIFOS  
FEATURES  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
Programmable Auto-RTS and Auto-CTS  
In Auto-CTS Mode, CTS Controls Transmitter  
– Break, Parity, Overrun, and Framing Error  
Simulation  
In Auto-RTS Mode, RCV FIFO Contents and  
Threshold Control RTS  
Fully Prioritized Interrupt System Controls  
Serial and Modem Control Outputs Drive a  
RJ11 Cable Directly When Equipment Is on  
the Same Power Drop  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
Capable of Running With All Existing  
TL16C450 Software  
Available in 48-Pin TQFP (PFB), 44-Pin PLCC  
(FN), or 32-Pin QFN (RHB) Packages  
After Reset, All Registers Are Identical to the  
TL16C450 Register Set  
Pin Compatible with TL16C752B (48-Pin  
Package)  
Up to 24-MHz Clock Rate for up to 1.5-Mbaud  
Operation With VCC = 5 V  
APPLICATIONS  
Point-of-Sale Terminals  
Gaming Terminals  
Portable Applications  
Router Control  
Cellular Data  
Factory Automation  
Up to 20-MHz Clock Rate for up to 1.25-Mbaud  
Operation With VCC = 3.3 V  
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation With VCC = 2.5 V  
In the TL16C450 Mode, Hold and Shift  
Registers Eliminate the Need for Precise  
Synchronization Between the CPU and Serial  
Data  
DESCRIPTION  
Programmable Baud Rate Generator Allows  
Division of Any Input Reference Clock by 1 to  
(216 - 1) and Generates an Internal 16 × Clock  
The TL16C2550 is a dual universal asynchronous  
receiver and transmitter (UART). It incorporates the  
functionality of two TL16C550D UARTs, each UART  
having its own register set and FIFOs. The two  
UARTs share only the data bus interface and clock  
source, otherwise they operate independently.  
Another name for the uart function is Asynchronous  
Communications Element (ACE), and these terms will  
be used interchangeably. The bulk of this document  
will describe the behavior of each ACE, with the  
understanding that two such devices are incorporated  
into the TL16C2550.  
Standard Asynchronous Communication Bits  
(Start, Stop, and Parity) Added to or Deleted  
From the Serial Data Stream  
5-V, 3.3-V, and 2.5-V Operation  
Independent Receiver Clock Input  
Transmit, Receive, Line Status, and Data Set  
Interrupts Independently Controlled  
Fully Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity Bit Generation and  
Detection  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (dc to 1 Mbit/s)  
False-Start Bit Detection  
Complete Status Reporting Capabilities  
3-State Output TTL Drive Capabilities for  
Bidirectional Data Bus and Control Bus  
Line Break Generation and Detection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the forma-  
tive or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the  
right to change or discontinue these products without notice.  
Copyright © 2005, Texas Instruments Incorporated  

TL16C2550 替代型号

型号 品牌 替代类型 描述 数据表
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