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TC74VHC9152P PDF预览

TC74VHC9152P

更新时间: 2024-11-12 01:06:31
品牌 Logo 应用领域
东芝 - TOSHIBA 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 214K
描述
9-Bit Schmitt Buffer (Inverter)

TC74VHC9152P 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.76
系列:AHC/VHC/H/U/VJESD-30 代码:R-PDIP-T20
长度:24.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:9功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:11.6 ns传播延迟(tpd):17.6 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:4.18 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

TC74VHC9152P 数据手册

 浏览型号TC74VHC9152P的Datasheet PDF文件第2页浏览型号TC74VHC9152P的Datasheet PDF文件第3页浏览型号TC74VHC9152P的Datasheet PDF文件第4页浏览型号TC74VHC9152P的Datasheet PDF文件第5页浏览型号TC74VHC9152P的Datasheet PDF文件第6页浏览型号TC74VHC9152P的Datasheet PDF文件第7页 
TC74VHC00F/FT/FK  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VHC00F,TC74VHC00FT,TC74VHC00FK  
Quad 2-Input NAND Gate  
TC74VHC00F  
TC74VHC00FT  
TC74VHC00FK  
The TC74VHC00 is an advanced high speed CMOS 2-INPUT  
NAND GATE fabricated with silicon gate C2MOS technology.  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
The internal circuit is composed of 3 stages including buffer  
output, which provide high noise immunity and stable output.  
An input protection circuit ensures that 0 to 5.5 V can be  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5 V to 3 V systems and two  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
Features  
High speed: t = 3.7 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 2 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Power down protection is provided on all inputs.  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
= 2 to 5.5 V  
CC (opr)  
Low noise: V  
= 0.8 V (max)  
OLP  
Pin and function compatible with 74ALS00  
Weight  
SOP14-P-300-1.27A  
: 0.18 g (typ.)  
TSSOP14-P-0044-0.65A : 0.06 g (typ.)  
VSSOP14-P-0030-0.50  
: 0.02 g (typ.)  
1
2012-02-29  

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