Datasheet > TC55VL818FFI-83

TC55VL818FFI-83

更新时间： 2024-09-19 20:06:23

品牌	Logo	应用领域
东芝 - TOSHIBA		静态存储器内存集成电路
页数	文件大小	规格书
21页	553K
描述
IC 512K X 18 STANDARD SRAM, 9 ns, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-100, Static RAM

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TC55VL818FFI-83 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-100	针数：	100
Reach Compliance Code：	unknown	风险等级：	5.84
最长访问时间：	9 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.7 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

TC55VL818FFI-83 数据手册

TC55VL818FFI-83

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM

DESCRIPTION

The TC55VL818FFI is a synchronous static random access memory (SRAM) organized as 524,288 words by 18

bits. NtRAM^TM(no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the transition from

a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are synchronized

with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced Input signal ;

the input from the address pins and all control pins except the OE and ZZ pins are loaded into the internal

registers on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available in the same

clock cycle as that in which ADV is asserted. Write operations are internally self-timed and are initiated by the

rising edge of CLK in the cycle in which ADV is asserted. The input from the address pins and all control pins

except the OE and ZZ pins are loaded into the internal registers on the rising edge of CLK in the cycle in which

ADV is asserted. Input data is loaded in the cycle following the cycle in which ADV is asserted. Byte Write

Enables ( BW1 to BW2 ) allow from one to two Byte Write operations to be performed. A 2-bit burst address

counter and control logic are integrated into this SRAM. The TC55VL818FFI uses a single power supply (3.3 V) or

dual power supplies (3.3 V for core and 2.5 V for output buffer) and is available in a 100-pin low-profile plastic QFP

(LQFP). The TC55VL818FFI guarantees −40° to 85°C operating temperature so it is suitable for use in wide

operating temperature system.

FEATURES

•

Organized as 524,288 words by 18 bits

Fast cycle time of 12 ns minimum (83 MHz maximum)

Fast access time of 9 ns maximum (from clock edge to data output)

No-turnaround operation with flow-through data output

2-bit burst address counter (support for interleaved or linear burst sequences)

Synchronous self-timed Write

Byte Write control

Snooze mode pin (ZZ) for power down

LVTTL-compatible interface

Single power supply (3.3 V) or Dual power supplies (3.3 V for core and 2.5 V for output buffer)

Available in 100-pin LQFP package (LQFP100-P-1420-0.65K ; pitch:0.65 mm, height:1.6 mm, weight:0.56 grams

(typical))

PIN ASSIGNMENT (TOP VIEW)

PIN NAMES

CLK

Clock Input

A0 to A18

Address Inputs

CE , CE2 , CE2 Chip Enable Inputs

99 97 95 93 91 89 87 85 83 81

100 98 96 94 92 90 88 86 84 82

A18

Output Enable Input

Write Enable input

V^DDQ

V^SSQ

V^DDQ

V^SSQ

I/O9

I/O8

I/O7

V^SSQ

V^DDQ

I/O6

I/O5

V^SS

BW1 to BW2 Byte Write Enable

I/O10

I/O11

V^SSQ

V^DDQ

I/O12

I/O13

V^SS

ADV

CKE

Address Advance Input

Clock Enable

Snooze Input

V^DD

V^SS

I/O1 to I/O18

MODE

Data Inputs/Outputs

Mode select Input

No Connection

V^DD

V^SS

I/O14

I/O15

V^DDQ

V^SSQ

I/O16

I/O17

I/O18

I/O4

I/O3

V^DDQ

V^SSQ

I/O2

I/O1

Not Usable

Power Supply for Core

Power Supply for Output Buffer

Ground for Core

V^SSQ

V^DDQ

V^SSQ

V^DDQ

DDQ

32 34 36 38 40 42 44 46 48 50

31 33 35 37 39 41 43 45 47 49

Ground for Output Buffer

SSQ

Note : NtRAM

and No-Turnaround Random Access Memory are

trademarks of Samsung Electronics Co., Ltd..

2003-02-20 1/21

12 3 4 5 6 7...21

中文翻译

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