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TC10GP PDF预览

TC10GP

更新时间: 2024-09-20 15:53:51
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟微控制器外围集成电路
页数 文件大小 规格书
2页 71K
描述
Microcontroller, 32-Bit, 66MHz, CMOS, PQFP208, 0.50 MM PITCH, PLASTIC, FQFP-208

TC10GP 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknownECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.56
Is Samacsys:N具有ADC:NO
地址总线宽度:32位大小:32
最大时钟频率:40 MHzDAC 通道:NO
外部数据总线宽度:32JESD-30 代码:S-PQFP-G208
长度:28 mmI/O 线路数量:24
端子数量:208最高工作温度:70 °C
最低工作温度:PWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
认证状态:Not Qualified座面最大高度:4.1 mm
速度:66 MHz最大供电电压:2.75 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

TC10GP 数据手册

 浏览型号TC10GP的Datasheet PDF文件第2页 
Advance Information  
The TC10GP is the industry’s first  
single-core 32-bit microcontroller-  
DSP based around the Infineon  
TriCore-1 architecture. The  
TC10GP implements the  
computational capabilities of  
DSPs alongside the most  
optimized price/performance  
implementation of a RISC  
load/store architecture. It is well-  
suited for a wide variety of real-  
time oriented embedded control  
systems.  
synchronous and asynchronous  
serial communication interfaces,  
a Peripheral Control Processor  
(PCP) for data transfers and  
peripheral control, general-  
purpose timers, and  
Other on-chip features of the  
TC10GP include a configurable  
memory SRAM/cache for both  
instruction and data,  
sophisticated on-chip debug and  
emulation capabilities.  
Unified 32-bit MCU-DSP core  
- Load/Store architecture  
- Dual 16x16 MACs  
Internal Flexible Peripheral  
Peripheral Control Processor  
(PCP)  
Interconnect (FPI) Bus  
- Small, programmable  
interrupt-driven  
microcontroller for data  
transfers and peripheral  
control  
- Includes instructions for  
DMA control and bit handling  
- 2-KByte parameter SRAM  
- 1-KByte code SRAM  
- 4G Bytes address range  
- Conditional execution of  
arithmetic, logical, jump  
External Bus Interface (EBU)  
- Demultiplexed address and  
data buses  
- DSP addressing modes  
- Fast context switching  
- Superscalar design with  
three pipelines  
- 4-GByte address range  
- 66 MHz (80 MHz planned)  
- 32-bit data bus  
- 24-bit address bus  
- Little endian operation  
- Four decoded chip selects  
- Emulation memory support  
- Memory controller (SDRAM,  
ROM, SRAM)  
Memory  
- 8/0-KByte instruction SRAM  
- 8/16-KByte instruction cache  
- 32/16-KByte data SRAM  
- 0/16-KByte data cache  
Timers  
- Two General-Purpose Timer  
Units with three configurable  
32-bit timers  
l/O Supply: 3.3V± 10%  
Serial Interfaces  
- Two asynchronous serial  
interfaces (UARTs)  
Core Logic: 2.5V± 10%  
- Watchdog Timer  
- System Timer  
208-pin P-FQFP package  
- One synchronous serial  
interface (SSC)  
Temperature range:  
Standard 0°C to 70°C  
Parallel Ports  
- Three 8-bit parallel ports  
On-chip Power Management  

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