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TAS3204PAG PDF预览

TAS3204PAG

更新时间: 2024-10-28 04:00:47
品牌 Logo 应用领域
德州仪器 - TI 消费电路商用集成电路
页数 文件大小 规格书
72页 1211K
描述
AUDIO DSP WITH ANALOG INTERFACE

TAS3204PAG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TFQFP, TQFP64,.47SQ针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:1.35Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G64
JESD-609代码:e4长度:10 mm
湿度敏感等级:4功能数量:1
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

TAS3204PAG 数据手册

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TAS3204  
AUDIO DSP  
WITH ANALOG INTERFACE  
www.ti.com  
SLES197APRIL 2007  
TERMINAL  
INPUT/  
PULLUP/  
DESCRIPTION  
OUTPUT(1)  
PULLDOWN(2)  
NAME  
NO.  
I2C1_SDA  
2
Digital I/O  
Slave I2C serial clock input. Normally connected to system micro.  
Master I2C serial control data interface input/output. Normally  
connected to EEPROM.  
I2C2_SCL  
64  
Digital Input  
I2C2_SDA  
LRCLK_IN  
63  
58  
51  
Digital I/O  
Digital Input  
Digital Output  
Master I2C serial clock input. Normally connected to EEPROM.  
Serial data input left/right clock for I2S interface  
Serial data output left/right clock for I2S interface  
Pulldown  
Pulldown  
LRCLK_OUT  
MCLK input is used in slave mode. MCLK_IN must be locked to  
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).  
MCLK_IN  
43  
48  
Digital Input  
MCLK_OUT1  
Digital Output  
12.288 MHz clock output. This output is valid even when reset is LOW.  
The frequency for this clock is 6.144 MHz/(n+1) where n is programable  
in the range 0 to 255. Default value is 1.024 MHz. This output is valid  
even when reset is LOW.  
MCLK_OUT2  
47  
Digital Output  
The frequency for this clock is 512 kHz/(n+1) where n is programmable  
in the range 0 to 255. Default value is 512 kHz. This output is valid  
even when reset is LOW.  
MCLK_OUT3  
MUTE  
46  
5
Digital Output  
Digital Input  
This pin needs to be programmed as mute pin in the application code.  
In has no function in default after reset.  
Pulldown  
Power down, active LOW. After successful boot, its function is defined  
by the boot code.  
PDN  
7
Digital Input  
N/A  
RESERVED  
RESET  
50  
62  
Pulldown  
Pullup  
Connect to ground.  
System reset input, active low. A system reset is generated by applying  
a logic LOW to this terminal.  
Digital Input  
Requires a 22-k(1%) external resistor to ground to set analog  
currents. Trace capacitance must be kept low.  
REXT  
27  
Analog Output  
SCLK_IN  
SCLK_OUT  
SDIN1/GPIO3  
SDIN2/GPIO4  
SDOUT1  
59  
52  
61  
60  
54  
53  
Digital Input  
Digital Output  
Digital I/O  
Serial data input bit clock for I2S interface  
Serial data output bit clock for I2S interface  
Serial data input #1 for I2S interface or programmable for GPIO #3  
Serial data input #2 for I2S interface or programmable for GPIO #4  
Serial data output #1 for I2S interface  
Pullup  
Pullup  
Digital I/O  
Digital Output  
Digital Output  
SDOUT2  
Serial data output #2 for I2S interface  
Analog mid supply reference. This pin must be decoupled with a 0.1-µF  
low-ESR capacitor and an external 10-µF filter cap.(4)  
VMID  
25  
Analog Output  
Voltage reference for analog supply. A pin-out of the internally  
regulated 1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter  
capacitor must be connected between this terminal and AVSS_PLL.  
This terminal must not be used to power external devices.(4)  
VR_ANA  
39  
Power  
Voltage reference for digital supply. A pin-out of the internally regulated  
1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter capacitor  
must be connected between this terminal and DVSS. This terminal  
must not be used to power external devices.(4)  
VR_DIG  
VR_PLL  
55  
10  
Power  
Power  
Voltage reference for DPLL supply. A pin-out of internally regulated  
1.8-V power supply. A 0.1-µF low-ESR capacitor and a 4.7-µF filter  
capacitor must be connected between this terminal and DVSS. This  
terminal must not be used to power external devices.(4)  
Band gap output. A 0.1-µF low ESR capacitor should be connected  
between this terminal and AVSS_PLL. This terminal must not be used  
to power external devices.(4)  
VREF  
26  
49  
Analog Output  
Digital Input  
Voltage regulator enable. When enabled LOW, this input causes the  
power-supply regulators to be enabled.  
VREG_EN  
XTAL_IN  
41  
42  
Digital Input  
Crystal input. A 24.576-MHz (512Fs) crystal should be used.  
Crystal output.  
XTAL_OUT  
Digital Output  
(4) If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling  
capacitors of equal value provide an extended high frequency supply decoupling.  
Submit Documentation Feedback  
Physical Characteristics  
9

TAS3204PAG 替代型号

型号 品牌 替代类型 描述 数据表
TAS3204PAGR TI

完全替代

AUDIO DSP WITH ANALOG INTERFACE

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