TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
I2C1_SDA
2
Digital I/O
Slave I2C serial clock input. Normally connected to system micro.
Master I2C serial control data interface input/output. Normally
connected to EEPROM.
I2C2_SCL
64
Digital Input
I2C2_SDA
LRCLK_IN
63
58
51
Digital I/O
Digital Input
Digital Output
Master I2C serial clock input. Normally connected to EEPROM.
Serial data input left/right clock for I2S interface
Serial data output left/right clock for I2S interface
Pulldown
Pulldown
LRCLK_OUT
MCLK input is used in slave mode. MCLK_IN must be locked to
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).
MCLK_IN
43
48
Digital Input
MCLK_OUT1
Digital Output
12.288 MHz clock output. This output is valid even when reset is LOW.
The frequency for this clock is 6.144 MHz/(n+1) where n is programable
in the range 0 to 255. Default value is 1.024 MHz. This output is valid
even when reset is LOW.
MCLK_OUT2
47
Digital Output
The frequency for this clock is 512 kHz/(n+1) where n is programmable
in the range 0 to 255. Default value is 512 kHz. This output is valid
even when reset is LOW.
MCLK_OUT3
MUTE
46
5
Digital Output
Digital Input
This pin needs to be programmed as mute pin in the application code.
In has no function in default after reset.
Pulldown
Power down, active LOW. After successful boot, its function is defined
by the boot code.
PDN
7
Digital Input
N/A
RESERVED
RESET
50
62
Pulldown
Pullup
Connect to ground.
System reset input, active low. A system reset is generated by applying
a logic LOW to this terminal.
Digital Input
Requires a 22-kΩ (1%) external resistor to ground to set analog
currents. Trace capacitance must be kept low.
REXT
27
Analog Output
SCLK_IN
SCLK_OUT
SDIN1/GPIO3
SDIN2/GPIO4
SDOUT1
59
52
61
60
54
53
Digital Input
Digital Output
Digital I/O
Serial data input bit clock for I2S interface
Serial data output bit clock for I2S interface
Serial data input #1 for I2S interface or programmable for GPIO #3
Serial data input #2 for I2S interface or programmable for GPIO #4
Serial data output #1 for I2S interface
Pullup
Pullup
Digital I/O
Digital Output
Digital Output
SDOUT2
Serial data output #2 for I2S interface
Analog mid supply reference. This pin must be decoupled with a 0.1-µF
low-ESR capacitor and an external 10-µF filter cap.(4)
VMID
25
Analog Output
Voltage reference for analog supply. A pin-out of the internally
regulated 1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and AVSS_PLL.
This terminal must not be used to power external devices.(4)
VR_ANA
39
Power
Voltage reference for digital supply. A pin-out of the internally regulated
1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter capacitor
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices.(4)
VR_DIG
VR_PLL
55
10
Power
Power
Voltage reference for DPLL supply. A pin-out of internally regulated
1.8-V power supply. A 0.1-µF low-ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices.(4)
Band gap output. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used
to power external devices.(4)
VREF
26
49
Analog Output
Digital Input
Voltage regulator enable. When enabled LOW, this input causes the
power-supply regulators to be enabled.
VREG_EN
XTAL_IN
41
42
Digital Input
Crystal input. A 24.576-MHz (512Fs) crystal should be used.
Crystal output.
XTAL_OUT
Digital Output
(4) If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling.
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Physical Characteristics
9