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TAS3308PZT

更新时间： 2024-11-25 04:00:47
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
11页 371K
描述
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

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TAS3308PZT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.1
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G100
JESD-609代码：e4长度：14 mm
湿度敏感等级：3功能数量：1
端子数量：100最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Consumer ICs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

TAS3308PZT 数据手册

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TAS3308  
DIGITAL AUDIO PROCESSOR  
WITH ANALOG INTERFACE  
www.ti.com  
SLES215A–FEBRUARY 2008–REVISED MARCH 2008  
1
FEATURES  
2
•
Audio Input/Output  
•
Audio Digital Signal Processor  
–
–
–
–
Up to Three Synchronous Serial Audio  
Inputs (6 Channels)  
–
–
–
–
–
Programmable Functionality  
135-MHz Operation  
Up to Two Synchronous Serial Audio  
Outputs (4 Channels)  
Left, RIght and I2S Input Data Formats: 16-,  
20-, or 24-Bit Data  
Left, Right and I2S Output Data Formats:  
16-, 20-, or 24-Bit Data  
48-Bit Datapath With 76-Bit Accumulator  
Hardware Single Cycle Multiplier (28 × 48)  
Two Memory Loads and One Memory Store  
Per Cycle  
–
–
–
Usable 1K Words Data RAM (48 Bit) and  
Usable 1K Coefficient RAM (28 Bit)  
–
–
64 × Fs Bit Clock Rate  
3.25K Words Instruction Program RAM  
(2.8K Words Available)  
24.576-MHz XTAL Input for Master Clock  
Modes and Clock Auto Detection  
360 mS at 48 KHz, 17,408 Words 24-Bit  
Delay Memory  
–
–
–
Slave Mode 256, 384, or 512 × Fs MCLKIN  
With Automatic Clock Rate Detection  
•
PWM Features  
Slave Mode 32-, 44.1-, and 48-kHz Fs With  
Auto Sample Rate Detection  
–
–
Proven PurePath Digital™ Technology  
Fourth-Order Chaotic Noise Shaper With  
Non-Linear Correction  
Master Mode – 48-kHz Fs 10 Multiplexed  
Stereo Analog Inputs Selectable Into One  
Stereo ADC. ADC Maximum Input Level: 1  
Vrms SE  
–
–
High-Quality DNR 105 dBA (Typical) PWM  
Performance  
Click and Pop Minimizing at Power  
Up/Down Using TI Patented Technology  
–
–
Three Stereo Differential PWM Outputs  
High-Quality DNR 100-dBA (Typical) ADC  
Channel Performance (2 Channels) With  
Master Mode Clock  
•
General Features  
–
–
Easy-to-Use Control Interface  
I2C Serial Control Master and Slave  
Interface  
–
–
High-Quality DNR 105-dBA (Typical) PWM  
Channel Performance (6 Channels)  
–
Control Interface Operational Without  
External MCLK Input  
One Single-Ended Analog Stereo Line  
Driver Output With 1 of 10 Selectable  
Inputs, 10-kΩ, 100=pF Drive Capability  
(Maximum Output Level: 1 Vrms)  
–
–
–
–
–
Single 3.3-V Power Supply  
Integrated Regulators  
100-Pin TQFP Package  
M8051 Device Controller  
–
Line-Out Supports Left/Right, Left/Left, and  
Right/Right Combinations  
Auto Clock and Serial Data Rate Detection  
and Automatic Device Configuration  
Without Audible Artifacts  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PurePath Digital is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
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